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23. CAN Module
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23.1.17 CANi Single-Shot Control Register (CiSSCTLR Register) (i=0, 1)
Figure 23.20 C0SSCTLR and C1SSCTLR Registers
According to the CAN Specification 2.0 Part B, if the arbitration lost or transmission error causes a
transmit failure, the microcomputer continues transmitting data until the transmission is completed. The
CiSSCTLR register determines whether or not, and from which slot, data is re-transmitted.
In single-shot mode, if the arbitration lost or transmission error causes a transmission failure, data is not
transmitted again. When the SSCj bit (j=0 to 15) is set to "1", the corresponding message slot j is in
single-shot mode.
CANi Single-Shot Control Register (i=0, 1)(1, 2)
Symbol
Address
After Reset(3)
C0SSCTLR
022116 - 022016
000016
C1SSCTLR
02A116 - 02A016
000016
RW
SSC15
SSC14
SSC13
SSC12
SSC11
SSC10
Message Slot 15 Single-Shot
Control Bit
SSC9
SSC8
SSC7
SSC6
SSC5
Message Slot 14 Single-Shot
Control Bit
Message Slot 13 Single-Shot
Control Bit
Message Slot 12 Single-Shot
Control Bit
Message Slot 11 Single-Shot
Control Bit
Message Slot 10 Single-Shot
Control Bit
Message Slot 9 Single-Shot
Control Bit
Message Slot 8 Single-Shot
Control Bit
Message Slot 7 Single-Shot
Control Bit
Message Slot 6 Single-Shot
Control Bit
Message Slot 5 Single-Shot
Control Bit
Message Slot 4 Single-Shot
Control Bit
Message Slot 3 Single-Shot
Control Bit
Message Slot 2 Single-Shot
Control Bit
Message Slot 1 Single-Shot
Control Bit
Message Slot 0 Single-Shot
Control Bit
SSC4
SSC3
SSC2
SSC1
SSC0
0: Single-shot mode not used
1: Use single-shot mode
Bit Name
Function
Bit
Symbol
RW
NOTES:
1. Set the CiSSCTLR register after the CiMCTLj register (j=0 to 15) in a slot, corresponding to the bit to
be changed, is set to "0016".
2.The CiSSCTLR register can be accessed only when the BANKSEL bit in the CiCTLR1 register is set to
"0" (message slot control register and single-shot register selected).
3. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
reset, supplying the clock to the CAN module, and setting the BANKSEL bit to "0".
b7
b0
b15
b8