REVISION HISTORY
Rev.
Date
Description
Page
Summary
C-9
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
204
Figure 16.10 Transmit and Receive Operation (2) Receive Timing modified
209
Table 16.9 Pin Settings in UART (2) modified
224
Table 16.21 Pin Settings in Special Mode 2 (2) modified
230
Table 16.27 Pin Settings in CGI Mode (2) modified
239
Figure 16.29 SIM Interface Operation modified
A/D Converter
243
Table 17.1 A/D Converter Specifications Explanation for A/D Conversion
Start Condition revised; Note 2 revised
245
Figure 17.2 AD0CON0 Register Note 5 modified
250
Table 17.2 One-shot Mode Specifications Explanation for Start Condition
revised
254
Figure 16.29 Trigger Select Function Settings modified; Note 2 added
Intelligent I/O
266
Figure 21.3 G1TB Register and G1BCR0 Register Note 2 added to G1BT
register
269
Figure 21.4 G1BCR1 Register Note 3 revised
271
Figure 21.6 G1TM0 to G1TM7 Registers and G1POCR0 to G1POCR7
Registers modified
274
Table 21.2 Base Timer Specificaitons Conditions added to Base Timer Reset
Condition; Explanation for Counter increment/decrement mode in Selectable
Function revised
278
Figure 21.12 Base Timer Operation in Two-phase Signal Processing Mode
Figure modified; Note 1 revised; Note 2 added
280
Table 21.5 Pin Settings for Time Measurement Function modified
283
Figure 21.15 Prescaler Function and Gate Function
284
Table 21.7 Pin Settings for Waveform Generation Function modified
285
Table 21.9 Single-phase Waveform Output Mode Specfications Specifica-
tions for Output Waveform revised; Note 2 added
286
Figure 21.16 Single-Phase Waveform Output Mode modified
287
Table 21.10 Phase-Delayed Waveform Output Mode Specifications Specifi-
cations for Output Waveform modified
288
Figure 21.17 Phase-Delayed Waveform Output Mode modified
289
Table 21.11 SR Waveform Output Mode Specifications Specifications for
Output Waveform modified; Notes 3, 4, 5 added
291
Figure 21.18 SR Waveform Output Mode modified
293
Figure 21.20 G0CR to G1CR Registers, G0RB to G1RB Registers modified
295
Figure 21.23 G0EMR to G1EMR Registers Note 1 revised
296
Figure 21.24 G0ETC to G1ETC Registers Note 1 revised
298
Figure 21.26 G0IRF Register Notes 1 and 2 revised