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| 型號(hào)： | M30245MC-XXXGP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁(yè)數(shù)： | 58/268頁(yè) |
| 文件大小： | 2520K |
| 代理商： | M30245MC-XXXGP |
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M30245 Group
I2C Bus interface mode
Rev.2.00
Oct 16, 2006
page 148 of 264
REJ03B0005-0200
UARTi Special Mode Register 2 (UiSMR2)
Bit 0 is the I2C mode select bit 2. Table 1.50 lists the control changes by bit when the I2C mode select bit is "1". Start
and stop condition detection timing characteristics are shown in Figure 1.107.
Table 1.50. Functions changed by I2C mode select bit 2
Function
IICM2=0
IICM2=1
Interrupt numbers 13, 15, 17, 19
factor
Acknowledge not detected (NACK)
UARTi transfer (rising edge of the
last bit)
Interrupt number 2, 8, 10, 21 factor
Acknowledge detected (ACK)
UARTi receive (falling edge of the
last bit)
DMA factor
Acknowledge detected (ACK)
UARTi receive (falling edge of the
last bit)
Data transfer timing from UART
receive shift register to receive buffer
Rising edge of the last bit of receive
clock
Rising edge of the last bit of receive
clock
UART receive/ACK interrupt request
generation timing
Rising edge of the last bit of receive
clock
Rising edge of the last bit of receive
clock
Figure 1.107. Start/stop condition detect timing characteristics
Set up time
Hold time
SCL
SDA
(Start condition)
SDA
(Stop condition)
3 to 6 cyles < set up time (Note)
3 to 6 cycles < hold time (Note)
Note: Cycle number shows main clock input oscillation frequency f(Xin) cycle number.
Bit 1 is the clock synchronizing bit. When this bit is set to "1", if the falling edge is detected at pin SCLi while the internal
SCL is "H", the internal SCL is changed to "L", the baud rate generator value is reloaded and the L sector count starts.
Also, while the SCLi pin is "L", if the internal SCL changes from "L" to "H", baud rate generator stops counting. If the SCLi
pin is "H", counting restarts. Because of this function, the UARTi transmit/receive clock takes the AND condition for the
internal SCL and SCLi pin signals. This function operates from the clock half period before the first rise of the UARTi
clock to the 9th rise. To use this function, select the internal clock as the transfer clock.
Bit 2 is the SCL wait output bit. When this bit is set to "1", output from the SCLi pin is fixed to "L" at the clock's 9th fall.
When set to "0", the "L" output lock is released. This bit is unavailable when SCLi is external clock.
Bit 3 is the SDA output stop bit. When this bit is set to "1", an arbitration lost generated. If the arbitration lost detection flag
is "1", the SDAi pin simultaneously becomes high impedance.
Bit 4 is the UARTi initialize bit. While this bit is set to "1", the following operations are performed when the start condition
is detected.
The transmit shift register is initialized and the content of the transmission register is transmitted to the transmission
shift register. Transmission starts with the first bit of the next input clock. However, the UARTi output value does not
change when the start condition is detected. It also doesn't change when the clock is input and when the first bit of data
is output.
The receive shift register is initialized and reception starts with the first bit of the next input clock.
The SCL wait output is set to "1". The SCLi pin becomes "L" level at the fall of the 9th bit of the clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30245MG | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MGGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGF | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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