M30245 Group
Serial Communication
Rev.2.00
Oct 16, 2006
page 129 of 264
REJ03B0005-0200
Figure 1.91. Serial I/O-related registers (3)
Bit Symbol
Function
(clock synchronous
serial I/O mode)
Function
(UART mode)
R W
Symbol
UiC1 (i = 0 to 3)
Address
03AD
16, 036D16, 033D16, 032D16
UARTi transmit/receive control register 1 (i= 0 to 3)
O
When reset
02
16
Bit Name
TE
TI
RE
RI
UiIRS
UiRRM
UiLCH
UiERE
Transmit enable bit
Transmit buffer empty
flag
Receive enable bit
Receive complete flag
UARTi transmit interrupt
cause select bit
UARTi continuous
receive mode enable bit
Data logic select bit
Error signal output
enable bit
0 : Transmit disabled
1 : Transmit enable
0 : Data present in transmit
buffer register
1 : No data present in
transmit buffer register
0 : Receive disabled
1 : Receive enabled
0 : No data packet in receive
buffer register
1 : Data packet in
receive buffer register
0 : Transmit buffer empty
(TI =1)
1 : Transmit buffer
completed ( TXEPT =1)
0 : Continuous receive
mode disabled
1 : Continuous receive
mode enabled
0 : No reverse
1 : Reverse
O
X
O
X
O
Set to "0"
0 : Output disabled
1 : Output enabled
Bit
Symbol
Function
(clock synchronous
serial I/O mode)
Function
(UART mode) R W
Symbol
UiC0 (i = 0 to 3)
Address
03AC
16, 036C16, 033C16, 032C16
UARTi transmit/receive control register 0 (i= 0 to 3)
O
Note 1: Set the corresponding port direction register to "0".
Note 2: UART2 transfer pin (TxD2:P70 and SCL2:P71) is N-channel open drain output. It cannot
be set to CMOS output.
Note 3: Valid only in clock synchronous serial I/O mode and 8-bit UART mode.
Note 4: The corresponding port register and port direction register are invalid.
When reset
08
16
Bit Name
CLK0
CLK1
CRS
TXEPT
CRD
NCH
(Note 2)
CKPOL
UFORM
BRG count source
select bit
CTS/RTS function
select bit
Transmit register
empty flag
CTS/RTS disable bit
Data output select bit
CLK polarity select bit
Transfer format
select bit (Note 3)
0 0 : f1 is selected
0 1 : f8 is selected
1 0 : f32 is selected
1 1 : Invalid
Valid when bit 4 = "0"
0 : CTS is selected (Note 1)
1 : RTS is selected (Note 4)
0 : Data present in transmit register
1 : No data present in transmit register
0 : CTS/RTS function enabled
1 : CTS/RTS function disabled
0 : TxDi/SDAi and SCLi pin is CMOS output
1 : TxDi/SDAi and SCLi pin is N-channel open drain output
0 : Transmit data is output at falling edge of
transfer clock and receive data is input at
rising edge
1 : Transmit data is output at rising edge of
transfer clock and receive data is input at
falling edge
0 : LSB first
1 : MSB first
b1 b0
O
X
O
Set to "0"
b7
b0
b1
b2
b3
b4
b5
b6
b7
b0
b1
b2
b3
b4
b5
b6
Set to "0"