![](http://datasheet.mmic.net.cn/30000/M30245MC-XXXGP_datasheet_2358670/M30245MC-XXXGP_80.png)
Rev.2.00
Oct 16, 2006
page 78 of 264
M30245 Group
Universal Serial Bus
REJ03B0005-0200
The CPU writes a "1" to the CLR_OUT_BUF_RDY bit after a data set has been unloaded from the buffer by the CPU
(updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags).
If the buffer has one more data set in it, the buffer status flags transition from 112 to 102 .
If the buffer has no more data set in it, the buffer status flags transition from 102 to 002 .
AUTO_CLR is enabled and continuous transfer mode disabled:
Single Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 002 to
112 after it has successfully received a data packet from the host.
The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 112 to 002 automatically when the data
packet has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
Double Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has
successfully received a data packet from the host.
If the buffer has only one data packet, the buffer status flags transition from 002 to 102 .
If the buffer has two data packets, the buffer status flags transition from 102 to 112 .
The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags automatically when a data packet has been
unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
If the buffer has one more data packet in it, the buffer status flags transition from 112 to 102 .
AUTO_CLR is enable and continuous transfer mode enabled:
Single Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 002 to
112 after it has successfully received a data set equal to its buffer size or a short packet from the host.
The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 112 to 002 automatically when the data
set has been unloaded from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
Double Buffer Mode:
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has
successfully received a data set equal to its buffer size or a short packet from the host.
If the buffer has only one data set, the buffer status flags transition from 002 to 102 .
If the buffer has two data sets, the buffer status flags transition from 102 to 112 .
The USB FCU updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags automatically when a data set has been unloaded
from the buffer by the CPU without the CPU writing a "1" to the CLR_OUT_BUF_RDY bit.
If the buffer has one more data set in it, the buffer status flags transition from 112 to 102.
If the buffer has no more data set in it, the buffer status flags transition from 102 to 002.