![](http://datasheet.mmic.net.cn/30000/M30245MC-XXXGP_datasheet_2358670/M30245MC-XXXGP_262.png)
M30245 Group
Usage Notes
Rev.2.00
Oct 16, 2006
page 260 of 264
REJ03B0005-0200
(6) Additional actions to take upon receipt of an EP0 interrupt are as follows (Refer to the flowchart in Figure 1.212):
Step #1: Is OUT_BUF_RDY (EP0CSR0) set?
[YES] => Go to Step #2.
[NO] => No special S/W action required. Go to Step #1 after the next EP0 interrupt.
Step #2: Is SETUP_END (EP0CSR5) set?
[YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, &
EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt.
[NO] => Go to Step #3.
Step #3: Read number of data bytes equal to the EP0 'Receive Byte Count', stored in EP0WC7-0, from EP0 OUT
FIFO. Is this the final DATA packet of a Control Write Transfer?
[YES] => Go to Step #4_0.
[NO] => Go to Step #5_0.
Step #4_0: Is SETUP_END (EP0CSR5) set?
[YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, &
EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt.
[NO] => Set CLR_OUT_BUF_RDY & SET_DATA_END (i.e., EP0CSR6 & EP0CSR9, respectively). [Also set
CLR_SETUP, if SETUP flag == '1'.] Go to Step #4_1.
Step #4_1: Is SETUP_END (EP0CSR5) set?
[YES] => Set SEND_STALL (EP0CSR12). Go to Step #6_0.
[NO] => Go to Step #1 after the next EP0 interrupt.
Step #5_0: Is SETUP_END (EP0CSR5) set?
[YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP_END, & SEND_STALL (i.e., EP0CSR6, EP0CSR11, &
EP0CSR12, respectively). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #1 after the next EP0 interrupt.
[NO] => Set CLR_OUT_BUF_RDY (i.e., EP0CSR6). [Also set CLR_SETUP, if SETUP flag == '1'.] Go to Step #5_1.
Step #5_1: Is SETUP_END (EP0CSR5) set?
[YES] => Set SEND_STALL (EP0CSR12). Go to Step #6_0.
[NO] => Go to Step #1 after the next EP0 interrupt.
Step #6_0: Are OUT_BUF_RDY & SETUP (EP0CSR0 & EP0CSR2) set?
[YES] => Go to Step #6_1.
[NO] => Go to Step #6_0 after the next EP0 interrupt.
Step #6_1: Is SETUP_END (EP0CSR5) set?
[YES] => Set CLR_OUT_BUF_RDY, CLR_SETUP, & CLR_SETUP_END (EP0CSR6, EP0CSR8 & EP0CSR11). Go
to Step #6_0 after the next EP0 interrupt.
[NO] => Set CLR_OUT_BUF_RDY & CLR_SETUP (EP0CSR6 & EP0CSR8), and clear SEND_STALL (EP0CSR12).
Go to Step #1 after the next EP0 interrupt.
(7) Writing to the USB Function Interrupt Clear Register (USBIC).
Writing to the USB Function Interrupt Clear Register (USBIC) to clear USB Function Interrupt Status bits requires
special consideration. Before performing this operation, the USB Function Interrupt Enable Register (USBIE)
should be cleared (i.e., all bits disabled). Upon completion of the write to USBIC, the value of USBIE just prior to
its clearing should be restored.