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M30245 Group
Usage Notes
Rev.2.00
Oct 16, 2006
page 254 of 264
REJ03B0005-0200
Stop Mode and Wait Mode
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(1) When returning from stop mode by hardware reset, RESET pin must be set to “L” level until main clock oscillation is
stabilized.
(2) When switching to either wait mode or stop mode, instructions occupying four bytes either from the WAIT instruction
or from the instruction that sets the all clock stop control bit to “1” within the instruction queue are prefetched and then
the program stops. So put at least four NOPs in succession either to the WAIT instruction or to the instruction that
sets the all clock stop control bit to “1”.
(3) When using low-speed mode and low power dissipation mode, set the WAIT peripheral function clock stop bit
(CM02) to “1” and do not shift to wait mode.
(4) When using fSYN as the internal system clock, change to f(XIN) before entering to stop mode (set bit 0 of the
frequency synthesizer control register to “0”).
Interrupts
Reading address 0000016
When maskable interrupt occurs, the CPU reads the interrupt information (the interrupt number and interrupt request
evel) in the interrupt sequence. The interrupt request bit of the interrupt written in address 0000016 will then be set to
“0”.
Do not read address 0000016 by software. Reading address 0000016 by software sets enabled highest priority
interrupt source request bit to “0”. Though the interrupt is generated, the interrupt routine may not be executed.
Setting the stack pointer
The value of the stack pointer immediately after reset is initialized to 000016. Accepting an interrupt before setting a
value in the stack pointer may cause program runaway. Be sure to set a value in the stack pointer before accepting
an interrupt.
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When using the NMI interrupt, initialize the stack pointer at the beginning of a program. Generating any interrupts
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including the NMI interrupt is prohibited for the first instruction immediately after reset.
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The NMI interrupt
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The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc with a pull-up resistor if unused. Do not go
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into stop mode when the NMI pin set to “L”.
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The NMI pin also serves as P85, which is exclusively an input. Reading the contents of the P8 register allows the pin
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value to be read. Reading this pin is only to be used for establishing the pin level when the NMI interrupt is input.
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Do not reset the CPU with the input to the NMI pin in the “L” state.
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Do not attempt to go into stop mode when the input to the NMI pin is in “L” state. When the input to the NMI is in “L”
state, CM10 is fixed to “0” thereby refusing to go into stop mode.
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Do not attempt to go into wait mode when the input to the NMI pin is in “L” state. When the input to the NMI pin is in
“L” state, the CPU stops but the oscillation does not. This action does not save power. When this occurs, the CPU is
returned to the normal state by a later interrupt.
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Signals input to the NMI pin require an “L” level of (2 clocks + 300nS) or more from the operation clock of the CPU.
External interrupt
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Either an “H” or “L” level of at least 250 ns width is necessary for the signal input to pins INT0 to INT2 regardless of
the CPU operation clock.
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When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to “1”. After chang-
ing the polarity, reset the interrupt request bit to “0”. Figure 1.208 shows the procedure for changing the INT interrupt
generate factor.