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參數(shù)資料
| 型號(hào)： | M30245MC-XXXGP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 0.50 MM PITCH, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 242/268頁 |
| 文件大?。?/td> | 2520K |
| 代理商： | M30245MC-XXXGP |
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Rev.2.00
Oct 16, 2006
page 73 of 264
M30245 Group
Universal Serial Bus
REJ03B0005-0200
EP0 OUT FIFO with control write continuous transfer mode enabled
The USB FCU updates the OUT_BUF_RDY flag to "1" after:
It has successfully received a data set equal to 128 bytes or a short packet from the host
OR
A control write status phase has started but there are pending OUT data packets in the buffer.
The CPU writes "1" to CLR_OUT_BUF_RDY after the data set has been unloaded from the FIFO by the CPU (updates
the OUT_BUF_RDY flag to "0").
Special note when using continuous transfer mode in control read request
In continuous transfer mode, the CPU can write multiple data packets to the data buffer before setting the
SET_IN_BUF_RDY to "1". The CPU must write the last data packet separately to the data buffer and sets the
SET_DATA_END bit. For example, if the buffer size=128 bytes, MAXP= 8 bytes, and the CPU sends 64 bytes of data to
the host, the CPU does the following:
Writes 7x8=56 bytes to the buffer;
Sets SET_IN_BUF_RDY=1;
After the 7 packets are successfully sent to host, the IN_BUF_RDY flag changes from "1" to "0";
Writes the last 8 bytes of data to the buffer;
Sets SET_IN_BUF_RDY="1" and SET_DATA_END to "1";
The CPU should not write all 64 bytes of data, and set the SET_IN_BUF_RDY and SET_DATA_END bits to "1" at the
same time.
Special note when using continuous transfer mode in control write request
Because the buffer can hold multiple data packets before generating an interrupt, two special cases should be taken
into consideration:
1. The SETUP_END flag usually indicates a premature completion of a control transfer. However, if the data field of a
control write is a multiple of MAXP but not a multiple of the buffer size, the SETUP_END flag may be set without causing
a premature completion of transfer. For example, if MAXP =8, buffer size = 128, wLength = 192 (a multiple of MAXP but
not the buffer size), the following occurs in continuous mode:
After receiving 16 8-byte packets, (128 bytes) from the host, an EP0 interrupt is generated to indicate to the CPU that data
unloading can start.
When the host completes sending the remainder of the data field (eight 8-byte packets) an EP0 interrupt is not gener-
ated because the buffer is not full and there is no short packet.
When the status phase starts (the host sends an IN token), OUT_BUF_RDY and SETUP_END are set. The
SETUP_END is set because the CPU is unaware of the end of the data phase, thus DATA_END is not set. Whenever
DATA_END is not set and the status stage starts, the protocol state machine will treat it as a premature completion
(data field is less than wLength) and sets the SETUP_END bit.
It is the users responsibility to determine the difference between a premature completion and a normal completion
(data field equals the wLength) when the CPU acknowledges a SETUP_END flag in continuous mode.
2. The device usually returns a stall handshake when the host sends more data than specified in the wLength field.
However, if a host sends more data than specified in wLength in the middle of a continuous transfer burst, the USB FCU
returns ACK to every packet it receives if there are no errors. In this case, when the firmware detects this kind of protocol
error, it must set CLR_OUT_PKT_RDY to "1" and set SEND_STALL to "1" so that the USB FCU returns STALL in the
subsequent data or status phase. For example, if MAXP = 8, buffer size = 128, wLength = 26, the following may occur:
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M30245FCGP | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
| M30260F3VGP | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M3A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30260M8A-XXXGP-U5 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP48 |
| M30263F6AFP-U7 | 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PDSO42 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M30245MG | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MGGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGF | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| M30245MG-XXXGP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
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