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MCP MEMORY
3
KBE00S009M-D411
Revision 1.0
May 2005
GENERAL DESCRIPTION
The KBE00S00
9
M is a Multi Chip Package Memory which combines 2Gbit Nand Flash Memory(organized with two pieces of 1G bit
Nand Flash Memory) and 512Mbit synchronous high data rate Dynamic RAM.(organized with two pieces of 256Mbit Mobile SDRAM)
2Gbit NAND Flash memory is organized as 256M x8 bits and 512Mbit SDRAM is organized as 4M x32 bits x4 banks.
In 2Gbit NAND Flash, its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program
operation can be performed in typical 200
μ
s on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-
bytes block. Data in the page can be read out at 50ns cycle time per byte. The I/O pins serve as the ports for address and data input/
output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition,
where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the
extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm.
The device is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable appli-
cations requiring non-volatility.
In 512Mbit SDRAM, Synchronous design make a device controlled precisely with the use of system clock and I/O transactions are
possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system applications.
The KBE00S00
9
M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power
consumption. This device is available in 137-ball FBGA Type.
FEATURES
<Common>
Operating Temperature : -25
°
C ~ 85
°
C
Package : 137-ball FBGA Type - 12x14mm, 0.8mm pitch
<NAND>
Power Supply Voltage : 2.5~2.9V
Organization
- Memory Cell Array : (256M + 8,192K)bits x 8bits
- Data Register : (512 + 16)bits x 8bits
Automatic Program and Erase
- Page Program : (512 + 16)bits x 8bits
- Block Erase : (16K + 512)Bytes
Page Read Operation
- Page Size : (512 + 16)Bytes
- Random Access : 15
μ
s(Max.)
- Serial Page Access : 50ns(Min.)
Fast Write Cycle Time
- Program time : 200
μ
s(Typ.)
- Block Erase Time : 2ms(Typ.)
Command/Address/Data Multiplexed I/O Port
Hardware Data Protection
- Program/Erase Lockout During Power Transitions
Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
- Data Retention : 10 Years
Command Register Operation
Intelligent Copy-Back
Unique ID for Copyright Protection
<Mobile SDRAM>
Power Supply Voltage : 1.7~1.95V
LVCMOS compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
EMRS cycle with address key programs.
All inputs are sampled at the positive going edge of the system
clock.
Burst read single-bit write operation.
Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
DQM for masking.
Auto refresh.
64ms refresh period (8K cycle).
Multi-Chip Package MEMORY
1G Bit (128Mx8) Nand Flash*2 / 256M Bit
(4Mx16x4Banks) Mobile SDRAM*2
Address configuration
Organization
Bank
Row
Column Address
16Mx32
BA0,BA1
A0 - A12
A0 - A8