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參數(shù)資料
| 型號： | KBE00S009M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Gb NAND x 2 + 256Mb Mobile SDRAM x 2 |
| 中文描述： | 1Gb的NAND × 2 256Mb的移動SDRAM × 2 |
| 文件頁數(shù)： | 13/86頁 |
| 文件大小： | 1898K |
| 代理商： | KBE00S009M |
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MCP MEMORY
13
KBE00S009M-D411
Revision 1.0
May 2005
CAPACITANCE
(
T
A
=25
°
C, V
CC
=2.7V, f=1.0MHz)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input/Output Capacitance
C
I/O
V
IL
=0V
-
20
pF
Input Capacitance
C
IN
V
IN
=0V
-
20
pF
VALID BLOCK
NOTE
:
1. This device may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program
factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction up to 1K Program/Erase
cycle.
3. Minimum 2,013 valid blocks are guaranteed for each contiguous 256Mb memory space.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
16,104
-
16,384
Blocks
AC TEST CONDITION
(TA=-25 to 85
°
C)
Parameter
Value
Input Pulse Levels
0.4V to 2.4V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
1.5V
Output Load
VccQ=2.7+/-10% : 1 TTL GATE and CL=30pF
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH.
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input (4 clocks)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input (4 clocks)
L
L
L
H
H
Data Input
L
L
L
H
X
Data Output
L
L
L
H
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
Program / Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
200
500
μ
s
Dummy Busy Time for Multi Plane Program
t
DBSY
1
10
μ
s
Number of Partial Program Cycles
in the Same Page
Main Array
Nop
-
-
1
cycle
Spare Array
-
-
2
cycle
Block Erase Time
t
BERS
-
2
3
ms
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