參數(shù)資料
型號(hào)： ISL5416EVAL1
廠商： Intersil Corporation
英文描述： Four-Channel Wideband Programmable DownConverter
中文描述： 四通道可編程寬帶下變頻器
文件頁數(shù)： 58/71頁
文件大小： 1128K
代理商： ISL5416EVAL1
58
Electrical Specifications
V
CCC
= Core supply: 1.8V
±
0.09V, V
CCIO
= IO’s supply: 3.3V
±
0.165V, T
A
= -40
o
C to 85
o
C Industrial
PARAMETER
SYMBOL
MIN
MAX
UNITS
INPUT AND CONTROL TIMING, CLOCK SKEW (FIGURE 11 AND 12)
CLKC Frequency
f
CLK
t
CH
t
CL
t
DS
t
DH
t
SYNCS
t
SYNCH
t
PDC
t
RW
t
RS
t
CKS1
t
CKS2
-
95
MHz
CLKC High
3
-
ns
CLKC Low
4
-
ns
Setup Time - Data Inputs, Input Enables to CLKX High
5.5
-
ns
Hold Time - Data Inputs, Input Enables to CLKX High
0
-
ns
Setup Time - SYNCInX to CLKC High
3
Hold Time - SYNCInX to CLKC High
0
CLKC to Output Valid - SYNCO
-
5
ns
RESET Pulse Width Low
5
-
ns
RESET Setup Time to CLKC High (Note 5)
5
-
ns
CLKX to CLKC skew 1 (FIGURE 12)
2.5
CLKX to CLKC skew 2 (FIGURE 12)
2.5
MICROPROCESSOR WRITE TIMING (
μ
P mode = 0, FIGURE 13)
P(15:0) Setup Time to Rising Edge of WR
t
PSW
t
PHW
t
ASW
t
AHW
t
CSW
t
CHW
t
WPWL
7.5
-
ns
P(15:0) Hold Time from Rising Edge of WR
-1
-
ns
A(2:0) Setup Time to Rising Edge of WR
8.5
-
ns
A(2:0) Hold Time from Rising Edge of WR
-2
-
ns
CE Setup Time to Rising Edge of WR
7
-
ns
CE Hold Time from Rising Edge of WR
-2
-
ns
WR Low Time
5
-
ns
MICROPROCESSOR READ TIMING (
μ
P mode = 0, FIGURE 14)
A(2:0) Hold Time from RISING Edge of RD (Note 7)
t
AHR
t
DV
t
RE
t
RD
t
CSF
t
CHR
t
RCY
-4
-
ns
A(2:0) to P(15:0) Data Valid Time
-
19
ns
RD Enable Time
-
8.5
ns
RD Disable Time (Note 6)
-
6
ns
CE Setup Time to Falling Edge of RD
2.5
-
ns
CE Hold Time from Rising Edge of RD (Note 6)
0
-
ns
READ Cycle Time (Note 7)
25
-
ns
MICROPROCESSOR WRITE TIMING (
μ
P MODE = 1, FIGURE 15)
P(15:0) Setup Time to Rising Edge of DSTRB
t
PSR
t
PHR
t
ASR
t
AHR
t
CSR
t
CHR
t
R/WSF
t
R/WHR
t
DW
8
-
ns
P(15:0) Hold Time from Rising Edge of DSTRB
-0.5
-
ns
A(2:0) Setup Time to Rising Edge of DSTRB
7.5
-
ns
A(2:0) Hold Time from Rising Edge of DSTRB
-1.5
-
ns
CE Setup Time to Rising Edge of DSTRB
8
-
ns
CE Hold Time from Rising Edge of DSTRB
-2
-
ns
R/W Setup Time to Falling Edge of DSTRB
0
-
ns
R/W Hold Time from Rising Edge of DSTRB
-1
-
ns
DSTRB Low Time
6
-
ns
MICROPROCESSOR READ TIMING (
μ
P MODE = 1, FIGURE 16)
A(2:0) Hold Time from RISING Edge of DSTRB (Note 7)
t
AHR
t
DV
-1
-
ns
A(2:0) to P(15:0) Data Valid Time
-
16
ns
ISL5416
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