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參數(shù)資料
| 型號： | ISL5416EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | 四通道可編程寬帶下變頻器 |
| 文件頁數(shù)： | 43/71頁 |
| 文件大?。?/td> | 1128K |
| 代理商： | ISL5416EVAL1 |
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43
14
TIME USING CLOCKS/SAMPLES.
Count intervals and delays using clocks or input enables.
1 = clocks.
0 = input enables.
13:11
UPPER LIMIT.
Upper attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
10:8
LOWER LIMIT.
Lower attenuator control limit, 0 to 42 dB in 6 dB steps.
000 = 0 dB.
111 = 42 dB.
7:4
NORMALIZATION SHIFT/DIVIDE SELECT.
Normalizing shifter control. Divides the integrated magnitude by 2
N
prior to threshold comparison:
accumulator input bits:
2
0
. . . 2
-15
accumulator output bits:
2
16
. . . 2
-15
0000 = select 2
1
to 2
-14
1111 = select 2
16
. . .to 2
1
3
ENABLE INPUT EXPONENT BITS.
Enable the exponent bits from the input to be added to the attenuation control bits and routed to the channel(s).
2
ENABLE RANGE CONTROL EXPONENT BITS.
Enable the attenuator control register (accumulator MSBs) bits to be added to the exponent bits from the input and routed to the
channel(s).
1
ENABLE RANGE CONTROL.
1 = enable the range control.
0 = disable the range control (including timers).
0
ENABLE RANGE CONTROL BITS
Enable changes in the attenuator control register (if this bit is cleared, the timers still run but changes to the register are inhibited.
NOTE:
The range control can be enabled by writing to bit 0 or bit 0 can be set by SYNCInX to start updates. See IWA = 0*05h. Timing reset
by SYNCInX is enabled by bits 0 and 16 of IWA = 0*05h.
TABLE 36. ADC RANGE CONTROL -- MAIN (IWA = 0*10h)
RESET STATE = 0x00000000h
(Continued)
P(31:0)
FUNCTION
TABLE 37. TIME SLOT PERIOD, DELAY FROM SYNCInX TO START OF INTEGRATION (IWA = 0*11h)
RESET STATE = 0x00000000h
THIS
CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
FUNCTION
31:16
SYNC DELAY.
Delay from SYNC (external or counter generated) to the start of integration. Range of delay is 1 to 65536, load with the desired value
minus 1. Delay in input samples or clocks as selected by bit 14, IWA = 0*10h.
15:0
SLOT PERIOD.
Time interval between counter generated SYNCs in samples or clocks as selected by bit 14, IWA = 0*10h. Range for period is 2 to
65536, load with period minus 1.
TABLE 38. NUMBER OF INTEGRATIONS PER SLOT, INTEGRATION TIME (IWA = 0*12h)
RESET STATE = 0x00000000h
THIS CONTROL IS SHARED FOR AIN/BIN AND FOR CIN/DIN
P(31:0)
FUNCTION
31:16
NUMBER OF INTEGRATIONS PER SLOT.
Number of input magnitude integration periods per slot. Range is 1 to 32768, load with number of integrations minus 1.
15:0
INTEGRATION TIME.
Number of input samples to average before making an upper or lower threshold decision in samples or clocks as selected by bit 14,
IWA = 0*10h. Range is 2 to 65536, load with samples minus 1.
ISL5416
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PDF描述 |
|---|---|
| ISL5416KIZ | Four-Channel Wideband Programmable DownConverter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL5416KI | 功能描述:上下轉(zhuǎn)換器 QUAD WIDEBAND DOWN CONVERTER, 256 CABGA RoHS:否 制造商:Texas Instruments 產(chǎn)品:Down Converters 射頻:52 MHz to 78 MHz 中頻:300 MHz LO頻率: 功率增益: P1dB: 工作電源電壓:1.8 V, 3.3 V 工作電源電流:120 mA 最大功率耗散:1 W 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PQFP-128 |
| ISL5416KIZ | 制造商:Intersil Corporation 功能描述:LEAD-FREE QUAD WIDEBAND DOWN CONVERTER, 256 CABGA - Trays 制造商:Intersil Corporation 功能描述:PB-FREE W/ANNEAL QUAD DIGITAL DOWNCONVER 制造商:Intersil 功能描述:QD WIDEB& DWN CNVRTR 256 CABGA |
| ISL54200 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:USB 2.0 High/Full Speed Multiplexer |
| ISL54200EVAL1Z | 功能描述:EVALUATION BOARD FOR ISL54200 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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