參數(shù)資料
型號： ISL5416EVAL1
廠商： Intersil Corporation
英文描述： Four-Channel Wideband Programmable DownConverter
中文描述： 四通道可編程寬帶下變頻器
文件頁數(shù)： 35/71頁
文件大?。?/td> 1128K
代理商： ISL5416EVAL1
35
For synchronization of the ISL5416 channels to system
timing and/or to the processing of other ISL5416 channels,
one synchronization output (SYNCO) and two
synchronization inputs (SYNCIn1 and SYNCIn2) are
provided. The SYNCO of one ISL5416 might be connected
to the SYNCIn1 of all the ISL5416s to allow the uP to
synchronously start or update parameters in all of the
ISL5416s. A write to IWA = 0005h also internally routes the
SYNCO to the SYNCIn1 input with the same delay as
connecting the SYNCO pin to the SYNCIn1 pin. For
alignment to system timing, the SYNCInX pins can be
connected to any one-clock-wide signal synchronous to
CLKC. A second synchronization input, SYNCIn2, is
provided to synchronize different channels to different event
or to allow the processor to control certain events and the
system timing to control others.
There are three resets to the ISL5416 -- the reset pin, the
chip hard reset (IWA = 0006h), and the soft channel reset
(IWA = *018h). The pin reset and chip hard reset have the
same effect. The soft channel reset only affects the selected
channel and does not reset the control registers, only the
slave (active) registers of master/slave pairs.
8
RESAMPLER NCO1 2X CARRY OUT
7
AGC COUNTER LOAD SIGNAL (SYNC and slot counter generated)
6
AGC END OF DELAY COUNTER
5
AGC LOOP GAIN SELECT SIGNAL
4
AGC UPDATE FORWARD GAIN SIGNAL
3
CARRIER NCO MSB (L.O. TEST POINT)
2:0
FIFO READ ADDRESS (2:0); (FIFO Depth, empty = 0)
TABLE 18. TESTOUT X(15:0) BUS SIGNALS (CAN BE OR’d WITH NORMAL OUTPUT ON XOUT BY SETTING BITS 23:20, GWA = 0002h)
TABLE 19. TEST INPUT STROBE (GWA = 0003h)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
STROBE. A write to this location generates a one-clock-wide test input enable (for use with the test input register).
TABLE 20. SYNCO (GWA = 0004h)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
STROBE. A write to this location generates a one-clock-wide pulse on the SYNCO pin.
TABLE 21. SYNCO WITH INTERNAL FEEDBACK (GWA = 0005h)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
STROBE. A write to this location generates a one-clock-wide pulse on the SYNCO pin that is also internally fed back to the
SYNCIn1 pin.
TABLE 22. CHIP HARD RESET VIA SOFTWARE (GWA = 0006h)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
RESET STROBE. Writing to this location generates a hardware reset, resetting all control registers. Identical function to the RESET
pin.
ISL5416
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