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| 型號： | ISL5416EVAL1 |
| 廠商： | Intersil Corporation |
| 英文描述： | Four-Channel Wideband Programmable DownConverter |
| 中文描述： | 四通道可編程寬帶下變頻器 |
| 文件頁數(shù)： | 42/71頁 |
| 文件大小： | 1128K |
| 代理商： | ISL5416EVAL1 |
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42
A/D Range Control Registers
The range control section monitors the output of the A/D and
adjusts the RF/IF gain to maintain a desired A/D output
range. The gain adjustments are in 6 dB steps. The levels,
adjustment rates, and gain to bit mapping are
programmable.
A code is programmed for output on the EOUT bus for each
of the eight states of the three MSBs of the attenuator control
register. These codes can be up to 8 bits, but if four gain
control sections are used, only four bits are available for
each gain control section. The routing of the gain control bits
to EOUT bits is done in IWA = 0001h.
The range control registers will be explained later in:
IWA = 0*09h - 0*16h and IWA = 0*19h - 0*1Dh
Direct addresses 4-7 have a sequenced read mode for
quickly reading I/Q output data, real time AGC gain, sampled
AGC gain, or range control data. The read order is
programmed in this register. The arrival of a new channel
output sample resets the read pointer to the first data type.
The rising edge of the RD signal (or DSTRB with RD/WR
high in uP mode 1) will advance the pointer for that channel
to the next data to get it set up at the interface for fast
access. The CLKO2 signal can be programmed as an
interrupt signal for this mode (see GWA = 0000h, bit 13) to
tell the processor when there is a new data. Alternatively, the
frame strobe signals from the channels can be used.
TABLE 35.
μ
P SEQUENCED READ MODE, READ ORDER SELECT (IWA = 0*0Ah)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31
1 = Generate an interrupt with each new data output for this channel.
30:28
READ EIGHT. See bits 3:0. Mask off the MSB of the code.
27:24
READ SEVEN. See bits 3:0.
23:20
READ SIX. See bits 3:0.
19:16
READ FIVE. See bits 3:0
15:12
READ FOUR. See bits 3:0
11:8
READ THREE. See bits 3:0
7:4
READ TWO. See bits 3:0
3:0
READ ONE. (FIRST READ).
0000 = AGC Gain -- sampled by a write to IWA = *010h
0001 = AGC Gain -- real time (updated with every I/Q)
0010 = Q(7:0), 8 zeros
0011 = Q(24:8)
0100 = I(7:0), 8 zeros
0101= I(24:8)
0110 = range control I&D (see IWA = 0*1Ch)
0111 = range accumulator (see IWA = 0*1Bh)
Note that the I/Q data will be rounded to the number of bits programmed in IWA = *001h bits 5:3, and the real time AGC data will have
the format selected in IWA = *001h, bits 2:0.
TABLE 36. ADC RANGE CONTROL -- MAIN (IWA = 0*10h)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:24
IMMEDIATE HOLD OFF.
Delay in clock cycles after the immediate threshold adjustment before another adjustment is allowed (00000000 = 1 clock delay). Load
with the desired value minus one.
23:16
UPDATE EXPONENT DELAY.
Delay in clock cycles from a change in the VGA value before it is added to the input exponent value. This should be set to equal the
RF/ADC plus the ISL5416 pipeline delays (6 clocks).
15
DISABLE ACCUMULATOR UPDATES.
1 = disable range control accumulator updates. uP can still load.
ISL5416
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