參數(shù)資料
型號(hào)： ISL5416EVAL1
廠商： Intersil Corporation
英文描述： Four-Channel Wideband Programmable DownConverter
中文描述： 四通道可編程寬帶下變頻器
文件頁數(shù)： 53/71頁
文件大?。?/td> 1128K
代理商： ISL5416EVAL1
53
TABLE 64. UPPER/LOWER GAIN LIMIT (IWA = *00Ah)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:16
UPPER LIMIT.
E E E E M M M M M M M M M M M M
01.MMMMMMMMMMMM * 2^EEEE
Example: A gain of 48 (33.6 dB) would be:
1.5 * 2
5
or 0101100000000000
15:0
LOWER LIMIT. Same weighting as upper limit.
TABLE 65. LOOP GAINS (1 & 2) (IWA = *00Bh)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:24
ATTACK 1. Loop gain value used for increasing signal levels (decreasing gain). Bits 31:28 are the exponent, bits 27:24 are the
mantissa. Loop gain is 0.MMMM * 2
EEEE
. A loop gain of 00000000 weights the error by 2
-19
to the input of the accumulator.
23:16
DECAY 1. Loop gain value used for decreasing signal levels (increasing gain).
15:8
ATTACK 2. Loop gain value used for increasing signal levels (decreasing gain). Bits 15:12 are the exponent, bits 11:8 are the
mantissa. Loop gain is 0.MMMM * 2
EEEE
. A loop gain of 00000000 weights the error by 2
-19
to the input of the accumulator.
7:0
DECAY 2. Loop gain value used for decreasing signal levels (increasing gain).
TABLE 66. AGC COUNTER PRELOADS 1 (IWA = *00Ch)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:16
SLOT PERIOD (IN CLOCKS). Sets the timing interval (slot period) counter period. The interval counter can be reset by SYNCInX
(see IWA = *000h) to align it to the system timing. Load with number of clocks minus 1.
15:0
DELAY (In Clocks). Sets the delay from the start of the timing interval (bits (31:16 above) to the start of the interval set in IWA =
*00Dh. Load with number of clocks minus 1.
TABLE 67. AGC COUNTER PRELOADS 2 (IWA = *00Dh)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:16
UNUSED.
15:0
ADJUSTMENT INTERVAL (In Clocks). Sets the length of the adjustment period for timed AGC changes. (when loop gain 2 is used
in timed and sampled modes). Load with number of clocks minus 1.
TABLE 68. AGC uP GAIN LOAD VALUE (IWA = *00Eh)
RESET STATE = 0x00000000h
P(31:0)
FUNCTION
31:16
UNUSED.
15:0
GAIN. This location allows the uP to set the AGC gain directly. If the gain loaded by the uP is outside the limits set in IWA = *00Ah,
it will be set to the limit value. To set a fixed gain, set the loop gains to zero and the limits to full scale (or set both limits to the desired
gain). Bit weightings are the same as for the limits: EEEE MMMM MMMM MMMM.
TABLE 69. AGC uP GAIN LOAD STROBE (IWA = *00Fh)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
STROBE. Writing to this location generates a strobe, synchronized to the clock, that updates the AGC with the gain value in register
IWA = *00Eh. The transfer can also be caused by a SYNCInX signal (see IWA = *000h).
TABLE 70. READBACK SAMPLE AGC GAIN AND MAGNITUDE (IWA = *010h)
RESET STATE = INACTIVE
N/A
FUNCTION
N/A
STROBE. Writing to this location copies the AGC loop filter accumulator contents to a holding register to stabilize it for reading by
the uP at direct addresses 4 - 7. (The magnitude is read at this location after the strobe. Magnitude bit weightings are: 2
2
. . . 2
-13
)
ISL5416
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