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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 84/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
84/92
IP100-DS-R03
May 27, 2003
BIT
2
BIT NAME
DisableMemBase
BIT DESCRIPTION
Disable Memory Base Address Register. DisableMemBase does not
correspond directly to any register accessible by the host system. If
DisableMemBase is a logic 1 during auto initialization of the IP100, the
MemBaseAddress register will be disabled. When disabled, the value
returned when the MemBaseAddress register is read is undefined.
D3 Cold Power Management Event. D3ColdPme corresponds to the
PmeSupport bit in the PowerMgmtCap register.
D1 Power State Support. D1Support corresponds to the D1Support bit in the
PowerMgmtCap register.
D2 Power State Support. D2Support corresponds to the D2Support bit in the
PowerMgmtCap register.
Power Management Event Enable. PmeEn corresponds to the PmeEn bit in
the PowerMgmtCtrl register.
Minimum Grant. MinGnt corresponds to bits 7 through 4 of the MinGnt register.
Maximum Latency. MaxLat corresponds to bits 5 through 1 of the MaxLat
register.
3
D3ColdPme
4
D1Support
5
D2Support
6
PmeEn
10..7
15..11
MinGnt
MaxLat
10.7.3 Data
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x05
Access Mode ................ Read Only
Width ............................ 16 bits
BIT
BIT NAME
15..0
Data
Data. Data corresponds to the Data register.
10.7.4 StationAddress
Class............................. EEPROM Data Format
Base Address ............... 0x00, address written to EepromCtrl register
Address Offset .............. 0x10, 0x11, 0x12
Access Mode ................ Read Only
Width ............................ 48 bits
BIT
BIT NAME
15..0
StationAddress0
Station Address 0. StationAddress0 (offset 0x10) corresponds to the
StationAddressWord0 field of the StationAddress register.
31..16
StationAddress1
Station Address 1. StationAddress1 (offset 0x11) corresponds to the
StationAddressWord1 field of the StationAddress register.
47..32
StationAddress2
Station Address 2. StationAddress2 (offset 0x12) corresponds to the
StationAddressWord2 field of the StationAddress register.
BIT DESCRIPTION
BIT DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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