參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁數(shù)： 55/92頁
文件大小： 2801K
代理商： IP100
IP100
10.4.23 RxDMABurstThresh
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x14
Default .......................... 0x08
Width ............................ 8 bits
RxDMABurstThresh register sets the threshold for receive DMA bus master requests by the IP100 based upon
the number of used bytes in the receive FIFO, in units of 32 bytes. When the used space exceeds the threshold,
the IP100 may make a receive DMA request on the PCI bus. However, if the used space exceeds the
RxDMAFrameLen field in the current RFD, the IP100 will make receive DMA bus request regardless of whether
the used space exceeds the RxDMABurstThresh or not. RxDMABurstThresh may be overridden by the urgent
request mechanism. See the PCI Bus Master Operation section for information about the relationship between
RxDMABurstThresh and RxDMAUrgentThresh. Any value less than 0x08 is invalid and is interpreted as 0x08.
BIT
BIT NAME
R/W
7..0
RxDMABurstThresh
R/W
Receive DMA Burst Threshold. The RxDMABurstThresh is the of 32
byte words which must be present in the receive FIFO prior to the
assertion of a receive DMA bus master request.
10.4.24 RxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x10
Default .......................... 0x00000000
Width ............................ 32 bits
RxDMAListPtr is the physical address of the current receive DMA Frame Descriptor in the Receive DMA List. A
value of 0x00000000 for RxDMAListPtr indicates that no more RFDs are available to accept receive frames.
RxDMAListPtr only points to addresses on 8-byte boundaries, so RFDs must be aligned on 8-byte physical
address boundaries. RxDMAListPtr may be written directly by the host system to point the IP100 to the head of a
newly created Receive DMA List. RxDMAListPtr is also updated by the IP100 as it processes RFDs in the
Receive DMA List. As the IP100 finishes processing a RFD, it loads RxDMAListPtr with the value from the
RxDMANextPtr field of the current RFD in order to move on to the next RFD in the Receive DMA List. If the IP100
loads a value of 0x00000000 from the current RFD, the receive DMA logic enters the idle state, waiting for a
non-zero value to be written to RxDMAListPtr. To avoid access conflicts between the IP100 and the host system,
the host system must set the RxDMAHalt bit in the DMACtrl register before writing to RxDMAListPtr.
BIT
BIT NAME
R/W
31..0
RxDMAListPtr
R/W
Receive DMA List Pointer. RxDMAListPtr is the physical address, on
a 8-byte boundary, of the current RFD in the Receive DMA List.
IP100-DS-R03
May 27, 2003
55/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
BIT DESCRIPTION
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