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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 12/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
12/92
IP100-DS-R03
May 27, 2003
HOST SYSTEM MEMORY
TxDMANextPtr
TxFrameControl
1st TxDMAFragAddr
1st TxDMAFragLen
2nd TxDMAFragAddr
2nd TxDMAFragLen
Last TxDMAFragAddr
Last TxDMAFragLen
1st Data Frag (Buffer)
TFD
2nd Data Frag (Buffer)
Last Data Frag (Buffer)
FIGURE 4: TxDMA Data Structure
The TFD format is covered in the Registers and
Data Structures section.
The resulting linked list of TFDs is referred to as the
TxDMAList, as shown in Figure 5.
HOST SYSTEM MEMORY
TFD1
TFD2
FIGURE 5: TxDMA List of Two TFDs
In the simple case of a single frame, the host
system must create a TFD within the host system
memory containing the addresses and lengths of
the fragments of data to be transmitted. The host
system must write zero into TxDMANextPtr since
this is the only frame. The host starts the TxDMA
Logic by writing the memory location (a non-zero
address) of the TFD into TxDMAListPtr register. The
TxDMA Logic begins transferring data into the
IP100.
The IP100 first fetches the fragment addresses and
fragment lengths from the TFD and writes them one
at a time into registers, which are used to control the
data transfer operations. If the TxDMA Logic
transfers more data than can fit into the TxFIFO, an
overrun will occur.
The TxDMAListPtr I/O register within the IP100
contains the physical address that points to the
head of the TxDMAList. TxDMAListPtr must point to
addresses which are on 8-byte boundaries. A value
of zero in the TxDMAListPtr register implies there
are no pending TFD’s for the IP100 to process.
Generally, it is desirable for the host system to
queue multiple frames. Multiple TFD’s are linked
together in a list by pointing the TxDMANextPtr of
each TFD at the next TFD. The last TFD in the
linked list should have a value of zero for it’s
TxDMANextPtr.
The TxDMA process returns to the idle state upon
detection of a zero value for TxDMANextPtr. When
a new frame is available to transfer, the host system
must write the address of the new TFD into the
TxDMANextPtr memory location of the last TFD,
and either set the TxEnable bit, or utilize the IP100’s
automatic polling capability. Using automatic polling,
the IP100 will monitor the TxDMANextPtr memory
location until a non-zero value is found at that
location in system memory. The TxDMAPollPeriod
register controls this polling function, which is
enabled
when
TxDMAPollPeriod
non-zero
value.
The
TxDMAPollPeriod determines the TxDMANextPtr
polling interval.
In response to a TxDMAComplete interrupt, when
data transfer by TxDMA is finished, the host
acknowledges the interrupt and returns the frame
data buffers to the system. In the case of a
multi-frame TxDMAList, multiple frames may have
contains
written
a
to
value
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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