參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 38/92頁(yè)
文件大小： 2801K
代理商： IP100
IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
38/92
IP100-DS-R03
May 27, 2003
BIT
BIT NAME
R/W
BIT DESCRIPTION
LED SIGNAL PIN
LEDPWRN
MODE 0
MODE 1
Continuous logic 0 when
power is applied.
Alternating logic 1/0
when frame transmission
in progress.
Continuous logic 0 when
Ethernet link is valid.
Alternating logic 1/0
when frame reception in
progress.
Continuous logic 0 when
the IP100 is configured
for full duplex operation.
Alternating logic 1/0
when the IP100 detects a
collision.
Continuous logic 0 when Ethernet link speed is
100Mbps, and continuous logic 1 when Ethernet link
speed is 10Mbps.
Reserved for future use.
Global Reset. When GlobalReset is a logic 1, the IP100 resets the
logic functions and registers specified by the DMA, FIFO, Network,
Host, and AutoInit bits (related to both the transmit and receive
processes as applicable). The LAN PCI Configuration Registers are
not affected by GlobalReset. GlobalReset is self-clearing.
Receive Reset. When RxReset is a logic 1 the IP100 resets all of the
receive logic functions and registers specified by the DMA, FIFO,
and Network bits. RxReset is self-clearing, and should not be used
after initialization except to recover from receive errors such as a
receive FIFO over run.
Transmit Reset. When TxReset is a logic 1 the IP100 resets all of
the transmit logic functions and registers specified by the DMA,
FIFO, and Network bits. TxReset is self clearing, and is required to
be used after a transmit underrun error.
DMA Reset. DMA selects (when a logic 1) or excludes (when a logic
0) the IP100 DMA functions and registers (see below) for/from reset
based on the value of the GlobalReset, RxReset, and TxReset bits.
The DMA bit is self-clearing.
FIFO Reset. FIFO selects (when a logic 1) or excludes (when a logic
0) the IP100 FIFO functions and registers for/from reset based on
the value of the GlobalReset, RxReset, and TxReset bits. The FIFO
bit is self-clearing.
Network Reset. Network selects (when a logic 1) or excludes (when
a logic 0) the IP100 network functions and registers for/from reset
based on the value of the GlobalReset, RxReset, and TxReset bits.
The Network bit is self-clearing.
Continuous logic 0 when
power is applied.
EOEN
Continuous logic 0 when
Ethernet link is valid.
Alternating logic 1/0
when frame reception or
transmission in progress.
Continuous logic 0 when
the IP100 is configured
for full duplex operation.
Continuous logic 1 when
the IP100 is configured
for half duplex operation.
LEDDPLXN
LEDSPDN
15
16
Reserved
GlobalReset
N/A
W
17
RxReset
W
18
TxReset
W
19
DMA
W
20
FIFO
W
21
Network
W
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