- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360868 > IP100 PCI 10/100M Single Chip Ethernet Controller PDF資料下載
參數(shù)資料
| 型號(hào)： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 58/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁當(dāng)前第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁
IP100
TxDMABurstThresh determines the threshold for when the IP100 makes transmit DMA bus master requests,
based upon the available space in the transmit FIFO. TxDMABurstThresh represents free space in the transmit
FIFO in multiples of 32 bytes. When the free space exceeds the threshold, the IP100 may make a transmit DMA
request. However, if the free space exceeds the current FragLen subfield of the TxFrameControl field within the
current TFD, the IP100 will make transmit DMA bus request regardless of whether the free space exceeds the
TxDMABurstThresh or not. TxDMABurstThresh may be overridden by the TxDMAUrgentThresh mechanism. See
the PCI Bus Master Operation section for information about the relationship between TxDMABurstThresh and
TxDMAUrgentThresh. Any value less than 0x08 is invalid and is interpreted as 0x08.
BIT
BIT NAME
R/W
4..0
TxDMABurstThresh
R/W
Transmit DMA Burst Threshold. The number of 32-byte words which
must be available in the transmit FIFO prior to assertion of a
transmit DMA Burst Request.
7..5
Reserved
N/A
Reserved for future use.
10.4.30 TxDMAListPtr
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x04
Default .......................... 0x00000000
Width ............................ 32 bits
TxDMAListPtr holds the physical address of the current transmit DMA Frame Descriptor in the transmit DMA list.
A value of zero in TxDMAListPtr is interpreted by the IP100 to mean that no more frames remain to be transferred
by transmit DMA. TxDMAListPtr can only point to addresses on 8-byte boundaries, so TFD’s must be aligned on
8-byte boundaries. TxDMAListPtr may be written directly by the host system to point the IP100 at the head of a
newly created transmit DMA list. Writes to TxDMAListPtr are ignored while the current value in TxDMAListPtr is
non-zero. To avoid access conflicts between the IP100 and the host system, the host system must set the
TxDMAHalt bit of the DMACtrl register to a logic 1 before writing to TxDMAListPtr (unless the host system has
specific knowledge that TxDMAListPtr contains zero).
BIT
BIT NAME
R/W
31..0
TxDMAListPtr
R/W
Transmit DMA List Pointer. TxDMAListPtr holds the physical address,
on a 8-byte boundary, of the current TFD in the transmit DMA list.
The host may examine the TxDMAListPtr to determine which
frame(s) have been transferred by transmit DMA. Those frames in
the transmit DMA list before the current TxDMAListPtr have already
been transferred by transmit DMA. If the TxDMAListPtr is zero, then
all the frames have been transmitted.
10.4.31 TxDMAPollPeriod
Class............................. LAN I/O Registers, DMA
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x0a
Default .......................... 0x00
Width ............................ 8 bits
TxDMAPollPeriod determines the interval at which the current TFD is polled. If the current TFDs, TxDMANextPtr
field is 0x00000000, the TxDMANextPtr field is polled to determine when a new TFD is ready to be processed.
Polling is disabled when TxDMAPollPeriod is 0x00. TxDMAPollPeriod represents a multiple of 320 ns time
intervals. The maximum value is 127 (or 40.64 us).
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
58/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
BIT DESCRIPTION
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。