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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 76/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.6.11 HeaderType
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x0e
Default .......................... 0x00 (single function)/0x80 (multi-function)
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
HeaderType
R
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
76/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
Header Type. If the Reserved/MultiFunction bit in the AsicCtrl
register is a logic 0, HeaderType is set to 0x00 identifying the IP100
as a single-function PCI device and specifying the configuration
register layout.
If the Reserved/MultiFunction bit in the AsicCtrl register is a logic 1,
HeaderType is set to 0x80 identifying the IP100 as a multi-function
PCI device and specifying the configuration register layout.
10.6.12 InterruptLine
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3c
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
InterruptLine
R/W
BIT DESCRIPTION
Interrupt Line. InterruptLine specifies the interrupt level used by the
IP100. By setting InterruptLine the host system may configure the
appropriate interrupt vector for its Interrupt Service Routine.
For 80x86 processor based host systems, InterruptLine corresponds
to the IRQ number (0x00 through 0x0F), with the value 0xFF
corresponding to disabled interrupts.
10.6.13 InterruptPin
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x3d
Default .......................... 0x01
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
InterruptPin
R
BIT DESCRIPTION
Interrupt Pin. InterruptPin indicates which PCI interrupt signal the
IP100 will utilize. The IP100 always utilizes the INTAN interrupt
signal, corresponding to an InterruptPin value of 0x01.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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