參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 34/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
10.3.4 PseudoPattern
Class............................. Wake Event Data Structures, Pseudo Packet
Base Address ............... Start of Pseudo Packet
Address Offset .............. 0x00 thru 0x00+n-1 for nth PseudoPattern
Access Mode ................ Write only
Width ............................ 8 bits
BIT
BIT NAME
3..0
ByteCount
ByteCount can take on a value of 0x0 to 0xe. A value of 0xf indicates an
extended value. The extended value will occupy 8 bits and is contained in the
next PseudoPattern. If both the ByteOffset and the ByteCount values are 0xf,
the next PseudoPattern will be the extended ByteOffset, and the
PseudoPattern after that will be the extended ByteCount.
7..4
ByteOffset
ByteOffset can take on a value of 0x0 to 0xe. A value of 0xf indicates an
extended value. The extended value will occupy 8 bits and is contained in the
next PseudoPattern. If both the ByteOffset and the ByteCount values are 0xf,
the next PseudoPattern will be the extended ByteOffset, and the
PseudoPattern after that will be the extended ByteCount.
10.3.5 Terminator
Class............................. Wake Event Data Structures, Pseudo Packet
Base Address ............... Start of Pseudo Packet
Address Offset .............. 0x00+n for n PseudoPattern
Access Mode ................ Write only
Width ............................ 8 bits
BIT
BIT NAME
7..0
Terminator
A value of 0x00 indicates the end of the PseudoPattern.
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
34/92
IP100-DS-R03
May 27, 2003
BIT DESCRIPTION
BIT DESCRIPTION
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