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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 53/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
BIT
12
IP100-DS-R03
May 27, 2003
53/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT NAME
RxDisable
R/W
W
BIT DESCRIPTION
Receive Disable. Writing a logic 1 to RxDisable will disable the
IP100 from receiving frames. The state (enabled/disabled) of the
IP100’s receiver is shown via RxEnabled.
Receive Enabled. If RxEnabled is a logic 1, the IP100’s receiver is
enabled.
Paused. If Paused is a logic 1, the IP100 has received a PAUSE
MAC Control Frame and the IP100 has halted the transmitter for the
duration indicated in the PAUSE Frame’s pause_time field. Paused
will become a logic 0 when the IP100’s transmitter ends is pause
operation.
Reserved for future use.
13
RxEnabled
R
14
Paused
R
15
Reserved
N/A
10.4.20 MaxFrameSize
Class............................. LAN I/O Registers, Control and Status
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x5a
Default .......................... 0x1514 or 0x4491 based on the RcvLargeFrames bit in the MACCtrl0 register
Width ............................ 16 bits
BIT
BIT NAME
R/W
15..0
MaxFrameSize
R/W
Maximum Frame Size. Received frames with sizes equal to or larger
than MaxFrameSize will be flagged as oversize via the
RxOversizedFrame bit in RxDMAStatus field of the frame’s RFD.
10.4.21 PhyCtrl
Class............................. LAN I/O Registers, External Interface Control
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x5e
Default .......................... 0x00
Width ............................ 8 bits
PhyCtrl contains control bits for the internal MII Management Interface. The MII Management Interface is used to
access registers in the IP100 PHY. The host system accesses the MII Management Interface by writing and
reading bit patterns to the PhyCtrl register.
BIT
BIT NAME
R/W
0
MgmtClk
R/W
Management Clock. MgmtClk drives the management clock (MDC)
signal to the PHY.
1
MgmtData
R/W
Management Data bit. MgmtData is directly connected to the MDIO
signal connected to the PHY. Data can be written to or read from the
PHY by writing or read MgmtData based on the value of MgmtDir.
2
MgmtDir
R/W
Management Data Direction. If the MgmtDir is a logic 1, the value
written to MgmtData is driven onto the MDIO signal connected to the
PHY. When MgmtDir is a logic 0, data driven onto MDIO by the PHY
can be read from MgmtData.
BIT DESCRIPTION
BIT DESCRIPTION
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PDF描述 |
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| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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