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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 17/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
IP100-DS-R03
May 27, 2003
17/92
Copyright
2003, IC Plus Corp.
All rights reserved.
IP100
determined by the D1Support bit in the
ConfigParm word in EEPROM. The D1 state
allows transition back to D0 with no delay. In
this state, the IP100 responds to PCI
configuration accesses, to allow the system to
change the power state. In D1 the IP100 does
not respond to any PCI I/O or memory
accesses. The IP100’s function in the D1
state is to recognize wake events and link
state events and pass them on to the system
by asserting the PMEN signal on the PCI bus.
D2 (power state 2) is a partial power-down
state. The IP100 optionally supports this state
determined by the D2Support bit in the
ConfigParm word in EEPROM. D2 allows a
faster transition back to D0 than is possible
from the D3 state. In this state, the IP100
responds to PCI configuration accesses, to
allow the system to change the power state.
In D2 the IP100 does not respond to any PCI
I/O or memory accesses. The IP100’s
function in the D2 state is to recognize wake
events and link state events and pass them
on to the system by asserting the PMEN
signal on the PCI bus.
D3 Hot (power state 3) is the full power-down
state for the IP100. In D3 Hot, the IP100 loses
all PCI configuration information except for
the value in PowerState. In this state, the
IP100
responds
to
accesses, to allow the system to change the
power state back to D0 Uninitialized. In D3 hot,
the IP100 does not respond to any PCI I/O or
memory
accesses.
responsibility in the D3 Hot state is to
recognize wake events and link state events
and signal those to the system by asserting
the PMEN signal on the PCI bus.
D3 Cold (power state undefined) is the
power-off state for the IP100. The IP100 does
not function in this state. When power is
restored, the system guarantees the assertion
of hardware reset, which puts the IP100 into
the D0 Uninitialized state.
The IP100 can generate wake events to the system
as a result of Wake Packet reception, Magic Packet
reception, or due to a change in the link status. The
WakeEvent register gives the host system control
over which of these events are passed to the
system. Wake events are signaled over the PCI bus
optionally
supports
this
state
PCI
configuration
The
IP100’s
main
using the PMEN pin.
A Wake Packet event is controlled by the
WakePktEnable
bit
in
WakePktEnable has no effect when IP100 is in the
D0 power state, as the wake process can only take
place in states D1, D2, or D3. When the IP100
detects a Wake Packet, it signals a wake event on
PMEN (if PMEN assertion is enabled), and sets the
WakePktEvent bit in the WakeEvent register. The
IP100 can signal that a wake event has occurred
when it receives a pre-defined frame from another
station. The host system transfers a set of frame
data patterns into the transmit FIFO using the
transmit DMA function before placing the IP100 in a
power-down state. Once powered down, the IP100
compares receive frames with the frame patterns in
the transmit FIFO. When a matching frame is
received (and also passes the filtering mode set in
the ReceiveMode register), a wake event is
signaled.
The frame patterns in the transmit FIFO specify
which bytes in received frames are to be examined.
Each byte in the transmit FIFO specifies a four bit
relative offset (from the start of the received frame)
in the most significant nibble and a four bit length
indicator in the least significant nibble. Relative
offsets describe the number of bytes of the received
frame to skip from the last relevant byte, beginning
with byte 0x00. Relative offsets with a value of 0xF
indicate the actual relative offset is larger than 15,
and is specified by the next 8 bit value in the
transmit FIFO. Length indicators with a value of 0xF
indicate the actual length indicator is larger than 15,
and is specified by the next 8 bit value in the
transmit FIFO. If both the relative offset, and the
length indicator are 0xF, the first byte following the
relative offset/length indicator pair is the actual
relative offset, and the second following byte is the
actual length indicator. A byte value of 0x00
indicates the end of the pattern for that wake frame.
Immediately following the end-of-pattern is a 4-byte
CRC. The calculation used to for the CRC is the
same polynomial as the Ethernet MAC FCS.
An example pseudo-packet (based on the ARP
packet example from Appendix A of the “OnNow
Network
Device
Class
Specification”) which would be loaded into the
transmit FIFO of the IP100 is shown in Figure 8.
WakeEvent
register.
Power
Management
Preliminary, Specification subject to change without notice.
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