參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 75/92頁(yè)
文件大?。?/td> 2801K
代理商： IP100
IP100
10.6.9 DeviceId
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x02
Default Value ................ 0x0201
Width ............................ 16 bits
BIT
BIT NAME
R/W
15..0
DeviceId
R
10.6.10 ExpRomBaseAddress
Class............................. LAN PCI Configuration Registers, Configuration
Base Address ............... PCI device configuration header start
Address Offset .............. 0x30
Default .......................... 0x00000000
Width ............................ 32 bits
ExpRomBaseAddress allows the system to define the base address for the adapter’s Expansion ROM.
ExpRomBaseAddress is disabled (read only with a value of 0x00000000) when the IP100 is in Multi-Function
Mode (see the Reserved/MultiFunction bit in the AsicCtrl register).
BIT
BIT NAME
R/W
0
AddressDecode-
Enable
IP100’s Expansion ROM is disabled. If AddressDecodeEnable is a
logic 1, and the MemorySpace bit in the ConfigCommand register is
a logic 1, the IP100 will respond to accesses to the expansion ROM
space.
14..1
Reserved
N/A
Reserved for future use.
31..15
RomBaseAddress
R/W
ROM Base Address. RomBaseAddress contains the expansion
ROM base address, or the upper 16 bits (or 15 bits, depending on
the state of the ExpRomSize bit in the AsicCtrl register) of the
Expansion ROM address range.
If the ExpRomSize bit in the AsicCtrl register is a logic 0, all 16 bits
of RomBaseAddress are valid. If the ExpRomSize bit in the AsicCtrl
register is a logic 1, bits 31 through 16 of RomBaseAddress are
valid, with bit 15 ignored (set to a logic 0) during write operations.
IP100-DS-R03
May 27, 2003
75/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
BIT DESCRIPTION
DeviceId contains the 16-bit device ID for the IP100.
BIT DESCRIPTION
R/W
Address Decode Enable. If AddressDecodeEnable is a logic 0, the
相關(guān)PDF資料
PDF描述
IP101 PHY 10/100M Single Chip Fast Ethernet Transceiver
IP1060AD Analog IC
IP1060AJ Voltage-Mode SMPS Controller
IP1060AN Analog IC
IP1060BJ Voltage-Mode SMPS Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IP1000A 制造商:IC PLUS 功能描述:IP1000A
IP1000ALF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R01 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R02 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
IP1000ALF-DS-R03 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*