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參數(shù)資料
| 型號(hào)： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 69/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
10.5.15 OctetsTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x6c
Default .......................... 0x00000000
Width ............................ 32 bits (accessible as 2, 16 bit words)
BIT
BIT NAME
19..0
OctetsTransmitted-
Ok
IP100-DS-R03
May 27, 2003
69/92
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
R/W
R/W
BIT DESCRIPTION
Octets Transmitted OK is a count of data and padding octets of
frames successfully transmitted. OctetsTransmittedOk will wrap
around to zero after reaching 0xFFFFFFFF. See IEEE 802.3 Clause
30.3.1.1.8.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when OctetsTransmittedOk reaches a value of
0xC0. OctetsTransmittedOk is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of OctetsTransmittedOk also clears the register.
Reserved for future use.
31..20
Reserved
N/A
10.5.16 SingleCollisionFrames
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset.............. 0x77
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
7..0
Single Collision
Frames
R/W
R/W
BIT DESCRIPTION
Single Collision Frames is a count of the number of frames that are
involved in a single collision, and are subsequently transmitted
successfully. SingleCollisionFrames will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.3.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when SingleCollisionFrames reaches a value of
0xC0. SingleCollisionFrames is enabled by writing a logic 1 to the
StatisticsEnable bit in the MACCtrl1 register.
A read of SingleCollisionFrames also clears the register.
相關(guān)PDF資料 |
PDF描述 |
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| IP101 | PHY 10/100M Single Chip Fast Ethernet Transceiver |
| IP1060AD | Analog IC |
| IP1060AJ | Voltage-Mode SMPS Controller |
| IP1060AN | Analog IC |
| IP1060BJ | Voltage-Mode SMPS Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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