參數(shù)資料
型號： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁數(shù)： 5/92頁
文件大小： 2801K
代理商： IP100
IP100
PIN DESCRIPTIONS
PIN NAME
PIN TYPE
PIN DESCRIPTION
PCI INTERFACE
RSTN
INPUT
Reset, asserted LOW. RSTN will cause the IP100 to reset all of its functional
blocks. RSTN must be asserted for a minimum duration of 10 PCICLK cycles.
PCI Bus Clock. This clock is used to drive the PCI bus interfaces and the
internal DMA logic. All bus signals are sampled on the rising edges of
PCICLK. PCICLK can operate from 0MHz to 33MHz.
PCI Bus Grant, asserted LOW. GNTN signals access to the PCI bus has been
granted to IP100.
Initialization Device Select. The IDSEL is used to select the IP100 during
configuration read and write transactions.
Interrupt Request, asserted LOW. The IP100 asserts INTAN to request an
interrupt, when any one of the programmed interrupt event occurs.
Wake Event, assertion level is programmable (see the WakePolarity bit of the
WakeEvent register). The IP100 asserts WAKE to signal the detection of a
wake event.
Request, asserted LOW. The IP100 asserts REQN to request PCI bus master
operation.
PCI Bus Address/Data. Address and data are multiplexed on the AD pins. The
AD pins carry the physical address during the first clock cycle of a transaction,
and carry data during the subsequent clock cycles.
PCI Bus Command/Byte Enable, asserted LOW. Bus command and byte
enables are multiplexed on the CBEN pins. CBEN specify the bus command
during the address phase transaction, and carry byte enables during the data
phase.
Parity. PCI Bus parity is even across AD[31..0] and CBEN[3..0]. The IP100
generates PAR during address and write data phases as a bus master, and
during read data phase as a target. It checks for correct PAR during read data
phase as bus master, during every address phase as a bus slave, and during
write data phases as a target.
PCI Bus Cycle Frame, asserted LOW. FRAMEN is an indication of a
transaction. It is asserted at the beginning of the address phase of the bus
transaction and de-asserted before the final transfer of the data phase of the
transaction.
Initiator Ready, asserted LOW. A bus master asserts IRDYN to indicate valid
data phases on AD[31..0] during write data phases, indicates it is ready to
accept data during read data phases. A target will monitor IRDYN.
Target Ready, asserted LOW. A bus target asserts TRDYN to indicate valid
read data phases, and to indicate it is ready to accept data during write data
phases. A bus master will monitor TRDYN.
Device Select, asserted LOW. The IP100 asserts DEVSELN when it is
selected as a target during a bus transaction. It monitors DEVSELN for any
target to acknowledge a bus transaction initiated by the IP100.
Stop, asserted LOW. STOPN is driven by the slave target to inform the bus
master to terminate the current transaction.
PCICLK
INPUT
GNTN
INPUT
IDSEL
INPUT
INTAN
OUTPUT
WAKE
OUTPUT
REQN
OUTPUT
AD
[31..0]
IN/OUT
CBEN
[3..0]
IN/OUT
PAR
IN/OUT
FRAMEN
IN/OUT
IRDYN
IN/OUT
TRDYN
IN/OUT
DEVSELN
IN/OUT
STOPN
IN/OUT
IP100-DS-R03
May 27, 2003
5/92
Copyright 2003, IC Plus Corp.
All rights reserved.
TABLE 2 : IP100 Pin Descriptions
Preliminary, Specification subject to change without notice.
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