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參數(shù)資料
| 型號： | IP100 |
| 英文描述： | PCI 10/100M Single Chip Ethernet Controller |
| 中文描述： | 單芯片的PCI個10/100M以太網(wǎng)控制器 |
| 文件頁數(shù)： | 62/92頁 |
| 文件大?。?/td> | 2801K |
| 代理商： | IP100 |
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IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
62/92
IP100-DS-R03
May 27, 2003
10.5 Statistic Registers
The Statistic registers implement several counters defined in the IEEE 802.3 standard. Note reading a statistic
register will also clear that register. The statistics gathering must be enabled by setting the StatisticsEnable bit in
MACCtrl1 for the statistics registers to count events.
10.5.1 BroadcastFramesReceivedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7d
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
BroadcastFrames-
ReceivedOk
frames that are successfully received with destination address equal
to
the
BroadcastFramesReceivedOk does not include frames received
with frames too long, FCS, length or alignment errors, or frames lost
due
to
internal
BroadcastFramesReceivedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.22.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when BroadcastFramesReceivedOk reaches a
value of 0xC0. BroadcastFramesReceivedOk is enabled by writing a
logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of BroadcastFramesReceivedOk also clears the register.
10.5.2 BroadcastFramesTransmittedOk
Class............................. LAN I/O Registers, Statistics
Base Address ............... IoBaseAddress register value
Address Offset .............. 0x7c
Default .......................... 0x00
Width ............................ 8 bits
BIT
BIT NAME
R/W
7..0
Broadcast-
FramesTransmitted-
Ok
(0xFFFFFFFFFFFF). Frames transmitted to other multicast
addresses
Broad-castFramesTransmittedOk will wrap around to zero after
reaching 0xFF. See IEEE 802.3 Clause 30.3.1.1.19.
An UpdateStats interrupt (UpdateStats bit within the IntStatus
register) will occur when BroadcastFramesTransmittedOk reaches a
value of 0xC0. BroadcastFramesTransmittedOk is enabled by
writing a logic 1 to the StatisticsEnable bit in the MACCtrl1 register.
A read of BroadcastFramesTransmittedOk also clears the register.
BIT DESCRIPTION
R/W
Broadcast Frames Received OK is the count of the number of
broadcast
address
(0xFFFFFFFFFFFF).
MAC
sublayer
error
(i.e.overrun).
BIT DESCRIPTION
R/W
Broadcast Frames Transmitted is the count of the number of frames
that are successfully transmitted to the broadcast address
are
excluded
from
this
statistic.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IP1000A | 制造商:IC PLUS 功能描述:IP1000A |
| IP1000ALF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R01 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R02 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
| IP1000ALF-DS-R03 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Gigabit Ethernet NIC Single Chip |
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