參數(shù)資料
型號(hào)： IP100
英文描述： PCI 10/100M Single Chip Ethernet Controller
中文描述： 單芯片的PCI個(gè)10/100M以太網(wǎng)控制器
文件頁(yè)數(shù)： 70/92頁(yè)
文件大小： 2801K
代理商： IP100
IP100
Copyright
2003, IC Plus Corp.
All rights reserved.
Preliminary, Specification subject to change without notice.
70/92
IP100-DS-R03
May 27, 2003
10.6 LAN PCI Configuration Registers
PCI based systems use a slot-specific block of configuration registers to perform configuration of devices on the
PCI bus. The configuration registers are accessed with PCI Configuration Cycles. The PCI bus supports two
types of Configuration Cycles. Type 0 cycles are used to configure devices on the local PCI bus. Type 1 cycles
are used to pass a configuration request to a PCI bus at a different hierarchical level. PCI Configuration Cycles
are directed at one out of eight possible PCI logical functions within a single physical PCI device. A IP100 based
PCI bus master device responds only to Type 0 Configuration Cycles, directed at function 0, or Type 1 cycles if an
external modem is attached. Type 1 cycles ( without a modem), and Type 0 cycles directed at functions other
than 0, are ignored by the IP100.
Each PCI bus device is required to decode 256 bytes of configuration registers. Of these, the first 64 bytes are
pre-defined by the PCI Specification. The remaining registers may be used as needed for PCI device-specific
configuration registers. In PCI Configuration Cycles, the host system provides a slot-specific decode signal
(IDSEL) which informs the PCI device that a configuration cycle is in progress. The PCI device responds by
asserting DEVSELN, and decoding the specific configuration register from the address bus and the byte enable
signals. See the PCI Expansion ROM specification for information on generating configuration cycles from driver
software.
Figure 14 shows the PCI configuration registers implemented by IP100. All locations within the 256-byte
configuration space that are not shown in the table, are not implemented and return zero when read.
BYTE 3
BYTE 2
BYTE 1
Data
PowerMgmtCap
NextItemPtr
MaxLat
MinGnt
InterruptPin
ExpRomBaseAddress
Subsystemld
SubsystemVendorld
CISPointer
MemBaseAddress
IoBaseAddress
HeaderType
LatencyTimer
ClassCode
ConfigStatus
Deviceld
BYTE 0
ADDR OFFSET
0x54
0x50
0x4c
0x48
0x44
0x40
0x3C
0x38
0x34
0x30
0x2C
0x28
0x24
0x20
0x1C
0x18
0x14
0x0C
0x08
0x04
0x00
PowerMgmtCtrl
Capld
InterruptLine
CapPtr
CacheLineSize
Revisionld
ConfigCommand
Vendorld
FIGURE 14 : IP100 PCI Register Layout
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