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參數(shù)資料
| 型號(hào)： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動(dòng)談判廣告登記（注冊(cè)4 [0x04]） |
| 文件頁(yè)數(shù)： | 6/66頁(yè) |
| 文件大?。?/td> | 1725K |
| 代理商： | ICSXXXXY |
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6
ICS1890
10M Serial Interface
The 10M Serial Interface is an alternative serial interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The 10M Serial interface provides the same
functionality, but with a serial data stream at a 10 MHz clock
rate.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode and by setting the 10/100SEL pin to 10
mode.
The 10M Serial Interface operation consists of a nine signal
interface: 10TCLK, 10TXEN, 10TD 10RCLK, 10RXDV, 10RD,
10CRS, 10COL, and LSTA.
Data is exchanged between the MAC and PHY serially at a 10
MHz clock rate.
Since only the 10M Serial Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for 10M Serial Interface functionality.
The pins have the following mapping:
MII
10M Serial
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
10TCLK
10TXEN
(1)
10TD
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
10RCLK
10RXDV
(1)
10RD
CRS
COL
LSTA
10CRS
10COL
LSTA
(1) Error generation and detection is not supported by
10Base-T.
Other mode configuration pins behave identically regardless
of which data interface is used.
Link Pulse Interface
The Link Pulse Interface is an alternative control interface
between the PHY and MAC/Repeater than the standard MII
Data interface. The Link Pulse provides detailed control over
the Auto-Negotiation process.
This interface is selected by setting the MII/SI pin to STREAM
INTERFACE mode, by setting the 10/100SEL pin to 10
mode, and by setting the 10/LP pin to LP mode.
The Link Pulse Interface consists of a five signal interface:
LTCLK, LPTX, LRCLK, LPRX, SD.
Since only the Link Pulse Interface or the MII Interface is
active at once, it is possible to share the MII Data interface
pins for Link Pulse Interface functionality.
The pins have the following mapping:
MII
Link Pulse
TXCLK
TXEN
TXER
TXD3
TXD2
TXD1
TXD0
LTCLK
LPTX
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
LRCLK
LPRX
CRS
COL
LSTA
SD
Other mode configuration pins behave identically
regardless of which data interface is used.
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