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參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 18/66頁 |
| 文件大?。?/td> | 1725K |
| 代理商： | ICSXXXXY |
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18
ICS1890
Register Access Rules
RO
CW
RW/0
RW
-
-
-
-
Read Only, writes ignored
Command Override Writable
Read/Write only logic zero
Read/Write
Four types of register access are supported by the device.
Read Only (RO) bits may be read, but writes are ignored.
Command Override Writable (CW) bits may be read, but writes
are ignored unless preceded by writing a logic one to the
Command Register Override bit (16:15). Read Write Zero (RW/
0) bits may be read, but must only be written with a logic zero
value. Writing a logic one to this type of bit may prevent the
device from operating normally. Read Write (RW) bits may be
read and may be written to any value.
Default Values
-
0
1
Pin
name
-
-
-
-
No default value
Default to logic zero
Default to logic one
Default depends on the state of the
named pin
Modifier
SC
LL
LH
-
-
-
Self Clearing
Latching Low
Latching High
Self clearing bits will clear without any further writes after a
specified amount of time. Latching bits are used to capture an
event. To obtain the current status of a latching bit, the bit
must be read twice in succession. If the special condition still
persists, the bit will be the same on the second read; otherwise,
the condition indication will not be present.
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