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參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動(dòng)談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 29/66頁 |
| 文件大小： | 1725K |
| 代理商： | ICSXXXXY |
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29
ICS1890
Extended Control Register (register 16
[0x10]
)
Extended Control Register (register 16)
The Control Register is a 16-bit read/write register used to pre-
program the
ICS1890
. At power-up and reset, this register
will be loaded to the default values specified in the table
above.
Command Register Override (bit 15)
If set to a logic one, this bit allows a subsequent write to any
Command Writeable bit (CW) in any register. A write to any
register after this bit is set will reset the bit, preventing
subsequent writes to Command Write able bits from having
any effect. Therefore, each write to a Command Writeable bit
must be preceded by writing a logic one to this bit.
Bits Reserved for ICS use (14-11)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits is unspecified and may be a logic zero or one.
PHY Address (Bits 10 through 6)
These five bits are used to indicate the address of the
ICS1890
on the management port of the MII (any number in
the range 0 - 31). The connection of the LEDs to the LED pins
sets the address. A read returns the address. A write is ignored.
Stream Cipher Scrambler Test Mode (Bit 5)
If set to a logic one, the scrambler will resynchronize after
252 bits of non-idle data instead of its normal time.
Bits Reserved for ICS use (Bit 4)
These bits are reserved for ICS use. These bits should only
be written as logic zero. Writing a logic one to these bits
may prevent the device from operating correctly.The
value of these bits is unspecified and may be a logic zero
or one.
NRZ/NRZ1 Encoding (bit 3)
When this bit is 1 normal NRZ1 encoding of data is performed
for 100Base-TX. When this bit is 0 NRZ coding is used
instead. NRZ encoding can be useful for system debug.
Invalid Error Code Test (bit 2)
If this bit is set to a logic one, the 4B5B encoder allows non-
data symbols to be sent when TXER is asserted. See the
Invalid Error Code Test table for the symbol mapping.
Reserved for ICS use (bit 1)
These bits are reserved for ICS use. These bits should only be
written as logic zero. Writing a logic one to these bits may
prevent the device from operating correctly. The value of
these bits in unspecified and may be a logic zero or one.
Stream Cipher Disable (bit 0)
If this bit is set to a logic one, the stream cipher encoder and
decoder are disabled. This will result in unscrambled IDLES
and data streams being transmitted and received for ease of
debug
Bit
Definition
When bit=0
When bit=1
Access
RW
/SC
RW /0
RW /0
RW /0
RW /0
RO
RO
RO
RO
RO
RW
RW /0
RW
RW
RW /0
RW
Default
Hex
15
Command Register Override
don’t allow writes to CW
bits
Read unspecified
Read unspecified
Read unspecified
Read unspecified
A
MII Management’s
Register Address code
0 - 31 Read Only
Read unspecified
normal
Read unspecified
NRZ
disabled
Read unspecified
enabled
allow next write to effect
both RW & CW bits
0
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
PHY address bit 4
PHY address bit 3
PHY address bit 2
PHY address bit 1
PHY address bit 0
Stream Cipher Scrambler Test Mode
Reserved for ICS
NRZ/NRZ1 Encoding
Invalid Error Code Test
Reserved for ICS
Stream Cipher Disable
-
-
-
-
P4RD
P3TD
P2LI
P1CL
P0AC
0
-
1
0
-
0
test mode
NRZ1
enabled
disabled
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