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參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 40/66頁 |
| 文件大?。?/td> | 1725K |
| 代理商： | ICSXXXXY |
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40
ICS1890
(1) 100Base-TX is a continuous transmission system and the
MAC/Repeater is responsible for sourcing IDLE symbols when
it is not transmitting data when using the Stream Interface.
(2) Since data is not framed when this interface is used, RXDV
has no meaning.
(3) Since the MAC/Repeater is responsible for sourcing both
active and idle data, the PHY can not tell when it is transmitting
in the traditional sense so collisions can not be detected.
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
The Transmit Clock (STCLK) is a continuous clock signal
generated by the
ICS1890
to synchronize the Transmit Data
lines. In the 100M Stream Interface mode, the
ICS1890
clock frequency is 25 MHz.
STCLK/(TXCLK)
Transmit Data 4
Transmit Data 4 (STD4) is the most significant bit and is
sampled continuously by the
ICS1890
synchronously with
the Transmit Clock.
STD4/(TXER)
Transmit Data 3
Transmit Data 3 (STD3) is sampled continuously by the
ICS1890
synchronously with the Transmit Clock.
STD3/(TXD3)
Transmit Data 2
Transmit Data 2 (STD2) is sampled continuously by the
ICS1890
synchronously with the Transmit Data Clock.
STD2/(TXD2)
Transmit Data 1
Transmit Data 1 (STD1) is sampled continuously by the
ICS1890
synchronously with the Transmit Clock.
STD1/(TXD1)
Transmit Data 0
Transmit Data 0 (STD0) (the least significant bit) is sampled
continuously by the
ICS1890
synchronously with the Transmit
Clock.
STD0/(TXD0)
Receive Clock
The Receive Clock (SRCLK) is sourced by the
ICS1890
.
There are two possible sources for the Receive Clock (SRCLK).
When a carrier is present on the receive pair, the source is the
recovered clock from the data stream. When no carrier is
present on the receive pair, the source is the Transmit Clock
(STCLK).
SRCLK/(RXCLK)
The Receive Clock frequency is 25 MHz in the 100M Stream
Interface mode.
Receive Data 4
Receive Error (SRD4) is the most significant bit of the receive
data nibble and is continuously asserted by the
ICS1890
.
SRD4/(RXER)
Receive Data 3
Receive Data 3 (SRD3) is continuously asserted by the
ICS1890
.
SRD3/(RXD3)
Receive Data 2
Receive Data 2 (SRD2) is continuously asserted by the
ICS1890
.
SRD2/(RXD2)
Receive Data 1
Receive Data 1 (SRD1) is continuously asserted by the
ICS1890
.
SRD1/(RXD1)
Receive Data 0
Receive Data 0 (SRD0) is the least significant bit of the receive
data nibble.
SRD0/(RXD0)
Carrier Sense
Carrier Sense is provided in the 100M Stream Interface mode
as a fast receive carrier look-ahead for optional application
use. Carrier is detected using the same circuitry used in the
MII Data Interface mode that is bypassed in this mode.
SCRS/(CRS)
The
ICS1890
asserts Carrier Sense (SCRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are non-idle in half duplex mode. SCRS is not
synchronous to either the transmit or receive clocks.
In full duplex mode and repeater mode, SCRS is asserted only
on receive activity.
Signal Detect
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
SD/(LSTA)
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