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參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 41/66頁 |
| 文件大小： | 1725K |
| 代理商： | ICSXXXXY |
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41
ICS1890
10M Serial Interface
10M Serial Interface - Pin Mapping
When the
ICS1890
is operating in the 10M Serial mode, the
MII Data Interface is remapped to accommodate the 10M
Serial Interface. The following table details the exact pin mapping.
Each individual pin description also contains the new 10M
Serial Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
MII
10M Serial
TXCLK
TXEN
TXER
TXD3
TXD2
XD1
TXD0
10TCLK
10TXEN
(1)
10TD
RXCLK
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
10RCLK
10RXDV
(1)
10RD
CRS
COL
LSTA
10CRS
10COL
LSTA
(1) Error generation and detection is not supported by 10Base-
T. Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the
ICS1890
to synchronize the Transmit Data
lines. In the 10M Serial Interface mode, the
ICS1890
clock
frequency is 10 MHz.
10TCLK/(TXCLK)
Transmit Enable
Transmit Enable (10TXEN) indicates to the
ICS1890
that the
MAC is sending valid data nibbles for transmission on the
physical media. Synchronous with its assertion, the
ICS1890
will begin reading the serial data on the transmit data line. The
ICS1890
terminates transmission of data following the de-
assertion of Transmit Enable.
10TXEN/(TXEN)
Transmit Data
Transmit Data 0 (10TD) is the serial transmit data bit and is
sampled continuously by the
ICS1890
synchronously with
the Transmit Clock.
10TD/(TXD0)
Receive Clock
The Receive Clock (10RCLK) is sourced by the
ICS1890
and
is 10 MHz in frequency. There are two possible sources for the
Receive Clock. When a carrier is present on the receive pair,
the source is the recovered clock from the data stream. When
no carrier is present on the receive pair, the source is the
Transmit Clock. In 10Base-T mode, the receive data pair will
be quiescent during periods of inactivity and the Transmit
Clock will be selected.
10RCLK/(RXCLK)
The
ICS1890
will only switch between clock sources when
Receive Data Valid is de-asserted. During the period between
Carrier Sense (CRS) being asserted and Receive Data Valid
being asserted, a clock phase change of up to 360 degrees
may occur. Following the de-assertion of Receive Data valid, a
clock phase of 360 degrees may occur.
Receive Data Valid
Receive Data Valid (10RXDV) is generated by the
ICS1890
.
It indicates that the
ICS1890
is recovering serial data on the
Receive Data (10RD) line synchronous with the Receive Data
Clock.
10RXDV/(RXDV)
The
ICS1890
asserts RXDV when it detects and recovers the
preamble or the start of stream delimiter (SSD) and de-asserts
it following the last data nibble or upon detection of a signal
error. RXDV is synchronous with the Receive Data Clock
(10RCLK).
Receive Data
Receive Data 0 (10RD) is the received serial data stream.
10RD/(RXD0)
Carrier Sense
The
ICS1890
asserts Carrier Sense (CRS) when it detects
that either the transmit or receive lines are non-idle in half
duplex mode. It is de-asserted when both the transmit and
receive lines are idle in half duplex mode. CRS is not synchronous
to either the transmit or receive clocks.
10CRS/(CRS)
In full duplex mode and repeater mode, CRS is asserted only
on receive activity.
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