- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360789 > ICSXXXXY Auto-Negotiation Advertisement Register (register 4 [0x04]) PDF資料下載
參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 34/66頁 |
| 文件大?。?/td> | 1725K |
| 代理商： | ICSXXXXY |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
34
ICS1890
Extended Control Register 2 (register 19
[0X13]
)
Extended Control Register 2 (register 19)
Node/Repeater Configuration (bit 15)
This bit directly reflects the status of the NOD/REP pin.
When this bit is logic zero, the device will default to Node
operation. SQE test will default to on. Carrier sense in half
duplex mode will be on transmit or receive activity.
When this bit is logic one, the device will default to Repeater
operation. SQE test will default to off. Carrier sense in half
duplex mode will be on receive activity only.
Hardware/Software Priority Status (bit 14)
This bit directly reflects the status of the HW/SW pin.
When this bit is logic zero, hardware pins have priority over
software settings. The 10/100SEL pin becomes an input and
controls speed selection. The DPXSEL pin becomes an input
and controls duplex selection. The ANSEL pin becomes an
input and chooses configuration with or without Auto-
Negotiation.
When configuration through Auto-Negotiation is selected,
the DPXSEL and 10/100SEL settings control the Auto-
Negotiation register 4 default settings and Auto-Negotiation
is enabled. When configuration without Auto-Negotiation is
selected, DPXSEL controls the duplex setting and 10/100SEL
controls the data rate setting.
When this bit is a logic one, software bits have priority over
hardware pin settings. The 10/100SEL pin becomes an output
indicating the link speed when LSTA the link is established
and parallels bit (17:15). The DPXSEL pin becomes an output
indicating the link duplex state when the link is established
and parallels bit (17:14). The ANSEL pin becomes an output
indicating whether auto-negotiation is being used and parallels
bit (0:12).
Bit
Definition
When bit=0
When bit=1
Access
Default
NOD/-
REP
HW/S-
W
Hex
15
Node/Repeater Mode
Node Mode
Repeater Mode
RO
14
Hardware/Software Priority
Hardware Priority
Software Priority
RO
13
Link Partner Supports
Remote Fault
Reserved for ICS
Reserved for ICS
Transmitted Remote Fault
Status
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
Reserved for ICS
A-N Power-up Remote Fault
Reserved for ICS
Reserved for ICS
Reserved for ICS
Automatic 100Base-TX
Power-down
unknown
partner supports Remote Fault
RO
0
12
11
Read unspecified
Read unspecified
RW /0
RW /0
-
-
10
RF bit in transmitted LCW=0
RF bit in transmitted LCW=1
RW /0
-
9
8
7
6
5
4
3
2
1
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Normal
Read unspecified
Read unspecified
Read unspecified
RW /0
RW /0
RW /0
RW /0
RW /0
RW
RW /0
RW /0
RW /0
-
-
-
-
-
0
0
-
0
Remote Fault on Power-up
0
Never Power-down automatically
Power-down automatically
RW
1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICX055ALA | AREA CCD IMAGE ARRAY |
| ICX055BLA | Optoelectronic |
| ICX056AK | AREA CCD IMAGE ARRAY |
| ICX056AKB | AREA CCD IMAGE ARRAY |
| ICX057AK | AREA CCD IMAGE ARRAY |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSXXXXYFLFT | 制造商:ICS 制造商全稱:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
| ICSXXXXYGLFT | 制造商:ICS 制造商全稱:ICS 功能描述:System Clock Chip for ATI RS400 P4TM-based Systems |
| IC-SY WK1D | 制造商:LASER COMPONENTS 功能描述:DEVELOPMENT KIT LD DRIVER |
| ICT-075-A-10.0-G | 制造商:Interconnect Devices Inc (IDI) 功能描述:contact probe, .075' CTR 3 amp, concave 90 deg |
| ICT-075-A-10-G S/C | 功能描述:觸點探頭 .075’ CTR 3AMP PROBE HEADED 90 DEG CNCAVE RoHS:否 制造商:IDI 類型:Probes 尖端類型:Spherical Radius 長度:8.26 mm 電流額定值:10 A 彈力:2.3 oz 行程:1.52 mm 系列:101050 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。