參數(shù)資料
型號(hào): ICSXXXXY
英文描述: Auto-Negotiation Advertisement Register (register 4 [0x04])
中文描述: 自動(dòng)談判廣告登記(注冊(cè)4 [0x04])
文件頁數(shù): 42/66頁
文件大?。?/td> 1725K
代理商: ICSXXXXY
42
ICS1890
Collision Detected
The
ICS1890
asserts Collision Detected (COL) when it
detects a receive carrier (non idle condition while transmitting
(TXEN asserted).
10COL/(COL)
In the 10 Mbps mode, the non-idle condition is detected by
monitoring the un-squelched receive signal. COL is not
synchronous to either the transmit or receive clocks.
In full duplex mode, COL is disabled and always remains low.
In the 10 Mbps Node mode, COL will also be asserted as part
of the signal quality error test (SQE). This behavior can be
suppressed with the SQE Test Inhibit bit (18:2).
Link Pulse Interface
Link Pulse Interface - Pin Mapping
When the
ICS1890
is operating in the Link Pulse mode, the
MII Data Interface is remapped to accommodate the Link
Pulse Interface. The following table details the exact pin mapping.
Each individual pin description also contains the new Link
Pulse Interface pseudo pin name followed by the real MII
Data Interface pin name that it is mapped onto.
MII
Link Pulse
TXCLK
TXEN
LPTX
TXD3
TXD2
XD1
TXD0
LTCLK
TXER
RXCL
RXDV
RXER
RXD3
RXD2
RXD1
RXD0
K LRCLK
LPRX
CRS
COL
LSTA
SD
Other mode configuration pins behave identically regardless
of which data interface is used.
Transmit Clock
The Transmit Clock (10TCLK) is a continuous clock signal
generated by the
ICS1890
with a frequency of 25 MHz.
LTCLK/(TXCLK)
Transmit Link Pulse
Data presented on this input will be transmitted as a Link Pulse
of approximately the same duration.
LPTX/(TXER)
Receive Clock
The Receive Clock (LRCLK) is sourced by the
ICS1890
and
is 25 MHz in frequency.
LRCLK/(RXCLK)
Receive Link Pulse
Receive activity that is qualified as a Link Pulse will be output
on this pin as a high level of approximately the same duration
as the Link Pulse.
LPRX/(RXER)
Signal Detect
This signal is asserted when the PLL detects 100Base-T activity
on the receive channel.
SD/(LSTA)
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