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參數(shù)資料
| 型號： | ICSXXXXY |
| 英文描述： | Auto-Negotiation Advertisement Register (register 4 [0x04]) |
| 中文描述： | 自動談判廣告登記（注冊4 [0x04]） |
| 文件頁數(shù)： | 19/66頁 |
| 文件大小： | 1725K |
| 代理商： | ICSXXXXY |
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19
ICS1890
Control Register (register 0
[0x00]
)
Control Register (register 0)
The control register is a 16-bit read/write register used to set
the basic configuration modes of the
ICS1890
. It is accessed
through the management interface of the MII.
Reset (bit 15)
Setting this bit to a logic 1 will reset the device and result in
the
ICS1890
setting all its status and control registers to their
default values. During this process the
ICS1890
may change
internal states and the states of physical links attached to it.
While in process, the bit will remain set and no other write
commands to the control register will be accepted. The reset
process will be completed within 500 ms and the bit will be
cleared indicating that the reset process is complete.
Loop Back (bit 14)
Setting this bit to a logic one causes the
ICS1890
to tristate
the transmit circuitry from sending data and the receive circuitry
from receiving data. The collision detection circuitry is also
disabled unless the collision test command bit is set. Data
presented to the MII transmit data path is returned to the MII
receive data path. The delay from the assertion of Transmit
Data Enable (TXEN) to the assertion of Receive Data valid
(RXDV) will be less than 512 bit times.
Bit
15
14
13
12
Definition
When bit=0
When bit=1
Access
RW/SC
RW
RW
RW
Default
0
0
1
1
Hex
Reset
Loopback
Data Rate
Auto-Negotiation Enable
no effect
disable loop back mode
10 Mb/s operation
disable Auto-Negotiation
reset the PHY
enable loop back mode
100 Mb/s operation
enable Auto-Negotiation
reduced power
consumption
3
11
Power-Down
normal mode
RW
0
0*
10
Isolate
no effect
isolate PHY from MII
RW
0 if PHY
Address > 0
1 if PHY
Address=0
0
0
0
0
0
0
0
0
0
0
9
8
7
6
5
4
3
2
1
0
Restart Auto-Negotiation
Duplex Mode
Collision Test
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
no effect
half duplex
no effect
always 0
always 0
always 0
always 0
always 0
always 0
always 0
restart Auto-Negotiation
full duplex
enable collision signal test
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
0
0
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