參數(shù)資料
型號(hào): HM17CM256
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 顯示驅(qū)動(dòng)器
英文描述: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, UUC580
封裝: 19.75 X 2.39 MM, GOLD BUMP, DIE-580
文件頁數(shù): 36/111頁
文件大?。?/td> 2094K
代理商: HM17CM256
HM17CM256
- 36 -
(19) LCD DRIVER CIRCUIT
This drive circuit generates four levels of LCD drive voltage. The circuit has 384 segment outputs
and 82 common outputs and outputs combined display data and FR signal.
Two of common outputs(COMI
0
,COMI
1
) are for pictograph marker display only. The common
drive circuit that has shift register and outputs common scan signals sequentially.
(20) DUMMY SEGMENT DRIVER CIRCUIT
Segment driver circuit has 6 dummy output ( SEGSA
0
~ SEGSA
3
, SEGSB
0
~ SEGSB
3
, SEGSC
0
~
SEGSC
3
) at each edge side. Normally, the segment driver output is generated by memorized
RAM data but there are no RAMs but registers for dummy segment driver. There are 8 bit registers
correspond to SEGSA
0
, SEGSB
0
, SEGSC
0
and drive LCD with same level to Y direction. ( SEGSA
1
~ SEGSA
3
, SEGSB
1
~ SEGSB
3
, SEGSC
1
~ SEGSC
3
are the same function. )
SEGSA
0
~ SEGSA
3
port is used same gradation palette with SEGA
0
~ SEGA
127
,
SEGSB
0
~
SEGSB
3
with SEGB
0
~ SEGB
127
, and SEGSC
0
~ SEGSC
3
with SEGC
0
~ SEGC
127
This circuit is effective at display of boundary or background display. The dummy segment
drivers do not depend on LREV polarity but ALLON and REV command for display
There are 4-byte registers for dummy segment driver, SEGSA
0
~ SEGSA
3
, SEGSB
0
~ SEGSB
3
,
SEGSC
0
~ SEGSC
3
, If you want to access this register, please use DMY =”1” command.
68 series
80 series
RS
DMY
R/W
RD
WR
0
0
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
0
There are the same rules at read out of dummy segment register as display RAM data read out
sequence. After address setting, the data of assigned address is shown directly after the end of
the read command, so pay attention that assigned data is available at 2nd timing step. In other
words, there needs 1 cycle dummy read after address set and write cycle.
1 cycle dummy read is necessary for after address setting and write cycle.
When access with DMY=”1”, X address is an effective value at address setting. There are 4-byte
and so 00
H
, 01
H
, 02
H
, 03
H
are effective at 8-bit mode and 00
H
, 01
H
are effective at 16-bit mode.
The access bears no relation to Y address setting.
When access with DMY=”1”, it is possible that the data is written into register by increment
operation.
notice) more detail information at
between Display RAM and address
Function
Read out display data
Write in display data
Read out dummy segment register
Write in dummy segment register
q
DUMMY SEGMENT REGISTER ADDRESS AND BITMAP
r
in
s
(10) Relation
t
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