
HM17CM256
- 11 -
I
PIN DESCRIPTION 2
No.
42
NAME
D
0
/SCL
I/O
I/O
FUNCTION
43
D
1
/SDA
I/O
44
D
2
/EXCS
I/O
45
D
3
/SMODE
I/O
46
D
4
/SPOL
I/O
47,48,49
D
5
,D
6
,D
7
I/O
When parallel interface is selected (P/S=”H”), data line is
connected to MPU data bus with 8bit bi-directional bus
When serial interface is selected (P/S=”L”),
D
0
and D
1
(SCL, SDA) are used as serial interface pins
and various sets are taken by serial interface use mode of
D
2
, D
3
, D
4
.
SDA : serial data input pin
SCL : data transfer clock
EXCS : extension chip selection I/O pin
SMODE : serial transfer mode setting input pin
SPOL : RS polarity selection pin when 3 line serial interface is
selected.
SDA data is shifted at the rising edge of SCL
Internal serial/parallel conversion into 8-bit data occurs at the
rising edge of 8
th
clock of SCL.
Set to “L” after data transfer or during non-access time
50,51,52,53
54,55,56,57
D
8
,D
9
,D
10
,D
11
,
D
12
,D
13
,D
14
,D
15
I/O
Connect to data bus to MPU with 8bit bi-directional bus.
Used as MSB 8bit data bus in the 16bit data RAM transfer
mode
Set to “L” or “H” when not used.
Chip selection pin.
Data in-out is possible when CS = “L”.
Input data selection pin.
Distinguish bus data from CPU whether instruction or display
data.
25
CS
I
RS
class
H
L
instruction
display data
26
RS
I
38
RD (E)
I
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
RD signal connection port of 80 series CPU.
Data bus goes to output state at RD = “L”.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Enable signal connection port of 68 series CPU.
Active status when this signal is at “H”.
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
WR signal connection port of 80 series CPU.
Active at “L” and data bus signal is taken at the rising edge
of WR.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Read write control signal , R/W connection port of 68-
series MPU.
R/W
H
status
read
L
write
37
WR (R/W)
I