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參數(shù)資料
| 型號(hào)： | HM17CM256 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 顯示驅(qū)動(dòng)器 |
| 英文描述： | 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC580 |
| 封裝： | 19.75 X 2.39 MM, GOLD BUMP, DIE-580 |
| 文件頁數(shù)： | 34/111頁 |
| 文件大?。?/td> | 2094K |
| 代理商： | HM17CM256 |
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HM17CM256
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(14) DISPLAY TIMMING GENERATOR
The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for
internal operation by inputting the original oscillating clock CK or by the oscillating circuit.
By setting up Master / Slave mode (M/S), the state of timing pulse pins and the timing generator
changes.
Display timing pulse pins and generator status
M/S port
mode
CL port
FR port
FLM port CLK port
L
Slave
Input
Input
Input
H
Master
Output
Output
Output
(15) SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT.
The latch signal from line counter clock to display data latch circuit is generated from display clock
(CL). Synchronized with the display clock, the line addresses of Display RAM are generated and
384-bit display data are latched to display-data latching circuit and then output to the LCD drive
circuit (SEG output port).
Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so
MPU can access it with no relationship with the read-out operation of the display data.
(16) GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM).
The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock
(CL). The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal
state ( inverse FR signal level per 1 frame ). But by setting up data (n-1) on n-line inversion
register and “1” on n-line alternated command (NLIN), n-line inverse waveform can be generated.
When this
HM17CM256
is used in multi-chip application, the signals of CL, FLM, FR and CLK
must be sent from master side to slave side.
(17) DISPLAY DATA LATCH CIRCUIT
This circuit latches the display data from display RAM to LCD driver circuit temporarily per every
common period. Normal / reverse display, display ON/OFF, and display all on command are done
by controlling data in this latch. And no data within display RAM changes.
Timing generator status
CL, FLM, FR signal generator stop
Operating status
Input
Output
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相關(guān)代理商/技術(shù)參數(shù) |
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| HM17CM4096 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM |
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| HM18-10001 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EE Style Common-Mode Chokes |
| HM18-10002 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EE Style Common-Mode Chokes |
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