參數(shù)資料
型號： HM17CM256
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 顯示驅(qū)動(dòng)器
英文描述： 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC580
封裝： 19.75 X 2.39 MM, GOLD BUMP, DIE-580
文件頁數(shù)： 29/111頁
文件大?。?/td> 2094K
代理商： HM17CM256
HM17CM256
- 29 -
(11) display data structure and gradation control
For the purpose of gradation control, information per pixel requires multiple bits. This IC has 3 bit
or 2 bit data per output to achieve the gradation display.
This IC is connected to an STN color LCD panel by three segment port units and one pixel consists
of three outputs of segment driver, and so 256 color ( 3 bits x 3 bits x 2 bits ) display on 128 x 82
pixels is realized.
Since one pixel data can be processed by one time access to memory, the data can be rewritten
fast and naturally.
The weight of each data bit is dependent on the status of SWAP register bit and REF register
when data is written to the display RAM.
ACCESS when (REF, SWAP)=(0, 0) or (1, 1)
notice) internal access X address :n
H
~7F
H
(access when REF=”0”)
:7F
H
~n
H
(access when REF=”1”)
ACCESS when (REF, SWAP)=(0, 1) or (1, 0)
notice) internal access X address :n
H
~7F
H
(access when REF=”0”)
:7F
H
~n
H
(access when REF=”1”)
SEGAi
SEGBi
h
i
j
k
Aj
Palette Bj
0
0
Palette Aj
1
0
0
SEGCi
Palette Cj
1
1
1
MSB LSB
MSB LSB
MSB
0
D
0
0
D
1
1
D
2
0
D
3
0
D
4
1
D
5
1
1
D
7
D
6
0
GLSB circuit
Gradation palette
j=0~7
i=0~127
CPU access data
X address :n
H
Gradation
control circuit.
Display RAM data
SEGAi
SEGBi
1
1
1
0
0
SEGCi
Palette Aj
Palette Bj
Palette Cj
1
0
0
MSB
LSB MSB
LSB MSB
0
D
0
0
D
1
1
D
2
0
D
3
0
D
4
1
D
5
1
1
D
7
D
6
Gradation palette
j=0~7
i=0~127
CPU access data
X address :n
H
Gradation
control circuit
Display RAM data
0
GLSB circuit
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