參數(shù)資料
型號： HM17CM256
廠商： HYNIX SEMICONDUCTOR INC
元件分類： 顯示驅動器
英文描述： 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
中文描述： LIQUID CRYSTAL DISPLAY DRIVER, UUC580
封裝： 19.75 X 2.39 MM, GOLD BUMP, DIE-580
文件頁數(shù)： 13/111頁
文件大?。?/td> 2094K
代理商： HM17CM256
HM17CM256
- 13 -
PIN DESCRIPTION 4
No.
NAME
I/O
O
FUNCTION
Segment drive port
Segment output from display RAM data
mode
Normal
Reverse
The output level is selected among V
LCD
, V
2
, V
3
, V
SS
by the
combination of FR signal and RAM data
(B/W mode)
Non-lighted
0
1
lighted
1
0
FR signal
V
LCD
V
2
display RAM data
Normal mode
Reverse mode
Dummy segment driver output
Located at both side of segment drivers, used for edge
display.
Common driver output
The output level is selected among V
LCD
, V
1
, V
4
and V
SS
by
the combination of FR and scan data.
V
2
V
3
V
SS
V
3
V
LCD
V
SS
174~557
SEGA
0
~SEGA
127
,
SEGB
0
~SEGB
127
,
SEGC
0
~SEGC
127
164~169,
562~567
SEGSA
0
~SEGSA
3
,
SEGSB
0
~SEGSB
3
,
SEGSC
0
~SEGSC
3
COM
0
~COM
79
O
Common drive output for icon display
Common drive output for icon display
External reference clock input pin
Open when using internal oscillator clock or used as slave
device.
In this case, OSC
1
goes to V
SS
level.
Connect external oscillating source to OSC
1
port or connect
resistor between OSC
1
and OSC
2
when using external
oscillator.
Input / output pin for display timing clock
Output clock from master device is applied to slave chip
through CLK pin when used as master / slave mode.
M/S
mode
H
master
output
L
slave
input*
*input from master chip’s CLK output
data
H
L
H
L
FR
H
H
L
L
Output level
V
SS
V
1
V
LCD
V
4
162~137,
132~119,
568~594,
3~15
O
163
16
65,
66
COMI
0
COMI
1
OSC
1
,
OSC
2
O
O
I
O
CLK
64
CLK
I/O
(port No. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595,596 is dummy port.)
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相關代理商/技術參數(shù)
參數(shù)描述
HM17CM4096 制造商:未知廠家 制造商全稱:未知廠家 功能描述:128XRGBX162 OUTPUT LCD DRIVER IC with built-in RAM
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HM18-10002 制造商:未知廠家 制造商全稱:未知廠家 功能描述:EE Style Common-Mode Chokes
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