參數(shù)資料
型號: HM17CM256
廠商: HYNIX SEMICONDUCTOR INC
元件分類: 顯示驅(qū)動器
英文描述: 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, UUC580
封裝: 19.75 X 2.39 MM, GOLD BUMP, DIE-580
文件頁數(shù): 16/111頁
文件大?。?/td> 2094K
代理商: HM17CM256
HM17CM256
- 16 -
Serial clock (SCL) should go to “L” at the non-access period and after 9bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent miss operation chip
selector state should be released (CS = “H”) after 9bit data transfer as shown in the following
figure
.
3line serial interface
(1-7) One systematization of CS when serial interface is selected
In the multi-chip operation (master/slave) mode with serial I/F connection, one CS signal
controls two chips to reduce control signal.
Connect extended chip selection port (EXCS) of master chip to EXCS port ( input at slave
device and output at master device mode ) of slave chip.
When EXCS is “L”, master chip cannot accept command except for EXCS control; at this
point, only slave chip can be controlled.
Slave device control is possible when CS = “L” period within EXCS = “L” state.
RS
D
7
D
6
D
5
D
4
D
3
D
2
D
1
1
2
3
4
5
6
7
8
CS
SDA
SCL
D
0
9
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
CS
(MASTER)
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
CS
(SLAVE)
CS
SDA
SCL
RS
EXCS: expand CS signal ( input port )
Master device : output port
Slave device : input port
(input port)
P/S=0: serial I/F
P/S=1: parallel I/F
P/S: parallel . serial selection port
(input port)
M/S=0: slave operation
M/S=1: master operation
M/S: master . slave selection port
(input port)
SMODE=0: 4 line serial I/F
SMODE=1: 3 line serial I/F
SMODE: serial I/Fmode selection port
(input port)
Access display RAM at SPOL=0:RS=0
Access display RAM at SPOL=1:RS=1
SPOL:command data bit polarity selection port
At 3 line serial I/F mode
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