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參數(shù)資料
| 型號： | HM17CM256 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 128XRGBX82 OUTPUT LCD DRIVER IC with built-in RAM |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, UUC580 |
| 封裝： | 19.75 X 2.39 MM, GOLD BUMP, DIE-580 |
| 文件頁數(shù)： | 20/111頁 |
| 文件大?。?/td> | 2094K |
| 代理商： | HM17CM256 |
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HM17CM256
- 20 -
(7) Window address assign of display RAM
This IC can be accessed to display RAM by window area designation in addition to access to
display RAM designated by X and Y address.
Through address space of all display address, specific area of RAM can be accessed by
designated two points.
The start point of two point addresses is assigned by normal X address and Y address register and
the end point of them is done by X end address and Y end address register value. Designated
inner addresses depend on WLS bit.
Read modified write action can be taken by AIM=“1”.
In case of using window area accessing mode, you must set start point X address, Y address in
sequence and end point X address, Y address in sequence after executing Win command (WIN=“1”,
auto increase mode AXI=“1”, AYI=“1”) and then access to Display RAM.
And set start point and end point not to be designated to access the outside of available address
area. Address set value should be taken to set AX
≤
EX ( end point of X address ) and AY
≤
EY
( end point of Y address ).
X direction
(X, Y)
address designation
Window display area
(8) display RAM data and LCD
Display RAM data related with one dot of LCD is dependent on REV register. Normal display and
reverse display by REV register are set up as follows.
TABLE
REV
Display
RAM data
0
L
normal
1
0
H
reverse
1
(9) Segment display output order/reverse set up
The order of display outputs, SEGA
0
, SEGB
0
, SEGC
0
to SEGA
127
, SEGB
127
, and can be reversed
by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing
IC when assembling an LCD panel module.
end address designation
(X, Y)
All display RAM area
Y
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