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| 型號： | CYP15G0101DXA-BBC |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 9/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G0101DXA-BBC |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 9 of 78
Embedded Memory
Each member of the PSI family contains two types of embed-
ded memory blocks. The channel memory block is placed at
the intersection of horizontal and vertical routing channels.
Each channel memory block is 4096 bits in size and can be
configured as asynchronous or synchronous Dual-Port RAM,
Single-Port RAM, Read-Only memory (ROM), or synchronous
FIFO memory. The memory organization is configurable as
4Kx1, 2Kx2, 1Kx4 and 512x8. The second type of memory
block is located within each LBC and is referred to as a cluster
memory block. Each LBC contains two cluster memory blocks
that are 8192 bits in size. Similar to the channel memory
blocks, the cluster memory blocks can be configured as 8Kx1,
4Kx2, 2Kx4 and 1Kx8 and can be configured as either asyn-
chronous or synchronous Single-Port RAM or ROM.
Cluster Memory
Each logic block cluster of the PSI device contains two 8192-
bit cluster memory blocks.
Figure 6
is a block diagram of the
cluster memory block and the interface of the cluster memory
block to the cluster PIM.
The output of the cluster memory block can be optionally reg-
istered to perform synchronous pipelining or to register asyn-
chronous read and write operations. The output registers con-
tain an asynchronous RESET, which can be used in any type
of sequential logic circuits (e.g., state machines)
There are four global clocks (GCLK[3:0]) and one local clock
available for the input and the output registers. The local clock
for the input registers is independent of the one used for the
output registers. The local clock is generated in the user-de-
sign in a macrocell or comes from an I/O pin
Cluster Memory Initialization
The cluster memory powers up in an undefined state, but is set
to a user-defined known state during configuration. To facilitate
the use of look-up-table (LUT) logic and ROM applications, the
cluster memory blocks can be initialized with a given set of
data when the device is configured at power-up. For LUT and
ROM applications, the user cannot write to memory blocks.
Channel Memory
The PSI architecture includes an embedded memory block at
each crossing point of horizontal and vertical routing channels.
The channel memory is a 4096-bit embedded memory block
that can be configured as asynchronous or synchronous Sin-
gle-Port RAM, Dual-Port RAM, ROM, or synchronous FIFO
memory.
Data, address, and control inputs to the channel memory are
driven from horizontal and vertical routing channels. All data
and FIFO logic outputs drive dedicated tracks in the horizontal
and vertical routing channels. The clocks for the channel mem-
ory block are selected from four global clocks and pin inputs
from the horizontal and vertical channels. The clock muxes
also include a polarity mux for each clock so that the user can
choose an inverted clock.
Dual-Port (Channel Memory) Configuration
Each port has distinct address inputs, as well as separate data
and control inputs that can be accessed simultaneously. The
inputs to the Dual-Port memory are driven from the horizontal
and vertical routing channels. The data outputs drive dedicat-
ed tracks in the routing channels. The interface to the routing
is such that Port A of the Dual-Port interfaces primarily with the
horizontal routing channel and Port B interfaces primarily with
the vertical routing channel.
.
Figure 6. Block Diagram of Cluster Memory Block
5:1
DIN[7:0]
D
Q
ADDR[12:0]
D
Q
Cluster PIM
D
Q
WE
W
P
Write
Control
Logic
1024x8
Asynchronous
SRAM
Read
Control
Logic
R
DOUT[7:0]
8
3
3
8
10
C
C
D
Q
GCLK[3:0]
Local CLK
5:1
R
RESET
GCLK[3:0]
C
2
Local CLK
3
2
3
C
C
C
C
C
C
C
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0403DXB | Physical Layer Devices |
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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