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參數(shù)資料
| 型號： | CYP15G0101DXA-BBC |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 62/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101DXA-BBC |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 62 of 78
Pin and Signal Description
Frequency Agile PSI
Name
Function
Signal Description
Standard Device Signals
CCLK
Config_Done
Data
GCLK0-3
CCE
GCTL0-3
IO/V
REF0
IO/V
REF1
IO/V
REF2
IO/V
REF3
IO/V
REF4
IO/V
REF5
IO/V
REF6
IO/V
REF7
IO
IO6/Lock
MSEL
Reconfig
Reset
TCLK
TDI
TDO
TMS
Output
Output
Input
Input
Output
Input
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Output
Input
Input
Output
Input
Configuration Clock for serial interface with the external boot PROM
Flag indicating that configuration is complete
Pin to receive configuration data from the external boot PROM
Global Input Clock signals 0 through 3
Chip select for the external boot PROM
Global Control signals 0 through 3
Dual function pin: I/O or Reference Voltage for Bank 0
Dual function pin: I/O or Reference Voltage for Bank 1
Dual function pin: I/O or Reference Voltage for Bank 2
Dual function pin: I/O or Reference Voltage for Bank 3
Dual function pin: I/O or Reference Voltage for Bank 4
Dual function pin: I/O or Reference Voltage for Bank 5
Dual function pin: I/O or Reference Voltage for Bank 6
Dual function pin: I/O or Reference Voltage for Bank 7
Input or Output pin
Dual function pin: I/O in Bank 6 or PLL lock output signal
Mode Select Pin
Pin to start configuration of PSI
Reset signal to interface with the external boot PROM
JTAG Test Clock
JTAG Test Data In
JTAG Test Data Out
JTAG Test Mode Select
Name
I/O Characteristics
Signal Description
Transmit Path Data Signals
TXPERA
TXPERB
TXPERC
TXPERD
LVTTL Output,
changes relative to
REFCLK
↑
[36]
Transmit Path Error. Active HIGH. When BIST is enabled for the specific transmit chan-
nel, BIST progress is presented on these outputs. Once every 511 character times (plus
a 16-character Word Sync Sequence when the receive channels are clocked by a com-
mon clock), the associated TXPERx signal will pulse HIGH for one transmit-character
clock period to indicate a complete pass through the BIST sequence.
These outputs also provide indication of a transmit Phase-Align Buffer underflow or
overflow. When the transmit Phase-Align Buffers are enabled (TXCKSEL
≠
LOW, or
TXCKSEL = LOW and TXRATE = HIGH), if an underflow or overflow condition is detect-
ed, TXPERx for the channel in error is asserted and remains asserted until either an
atomic Word Sync Sequence is transmitted or TXRST is sampled LOW to re-center the
transmit Phase-Align Buffers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0403DXB | Physical Layer Devices |
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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