參數(shù)資料
型號(hào)： CYP15G0101DXA-BBC
元件分類： 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述： Telecomm/Datacomm
中文描述： 電信/數(shù)據(jù)通信
文件頁(yè)數(shù)： 42/78頁(yè)
文件大?。?/td> 1555K
代理商： CYP15G0101DXA-BBC
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 42 of 78
REFCLK Switching Characteristics
Transmit Serial Outputs and TX PLL Characteristics
Parameter
Description
Min.
Max.
Unit
f
REF
t
REFCLK
t
REFH
REFCLK Clock Frequency
10
150
MHz
REFCLK Period
6.6
100
ns
REFCLK HIGH Time (TXRATE = HIGH)
5.9
70
ns
REFCLK HIGH Time (TXRATE = LOW)
2.9
35
ns
t
REFL
REFCLK LOW Time (TXRATE = HIGH)
5.9
70
ns
REFCLK LOW Time (TXRATE = LOW)
2.9
35
ns
t
REFD[23]
t
REFR[19, 20, 21]
t
REFF[19, 20, 21]
t
TREFDS
t
TREFDH
t
RREFDA
t
RREFDH
t
REFADS
t
REFADH
t
REFCDS
t
REFCDH
t
REFRX
REFCLK Duty Cycle
30
70
%
REFCLK Rise Time (20%-80%)
0.3
5
ns
REFCLK Fall Time (20%-80%)
0.3
5
ns
Transmit Data or TXRST Setup Time to
REFCLK (TXCKSEL
=
LOW)
Transmit Data or TXRST Hold Time from REFCLK
(TXCKSEL
=
LOW)
Receive Data Access Time from REFCLK (RXCKSEL
=
LOW)
Receive Data Hold Time from REFCLK
(RXCKSEL
=
LOW)
1.5
ns
1
ns
9.5
ns
4.0
ns
Received Data Setup Time to RXCLKA (RXCKSEL = LOW)
2
ns
Received Data Hold Time from RXCLKA (RXCKSEL = LOW)
1.5
ns
Received Data Setup Time to RXCLKC (RXCKSEL = LOW)
3
ns
Received Data Hold Time from RXCLKC (RXCKSEL = LOW)
REFCLK Frequency Referenced to Received Clock Period
[23]
0.5
ns
0.02
+0.02
%
Parameter
Description
Condition
Min.
Max.
Unit
t
B
t
RISE
Bit Time
CML Output Rise Time 20
80% (CML Test Load)
[18]
5000
660
ps
SPDSEL = HIGH
50
250
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
FALL
CML Output Fall Time 80
20% (CML Test Load)
[18]
SPDSEL = HIGH
50
250
ps
SPDSEL = MID
100
500
ps
SPDSEL = LOW
200
1000
ps
t
DJ
t
RJ
t
TXLOCK
Deterministic Jitter (peak-peak)
[18, 24]
Random Jitter (
σ
)
[18, 25]
0.1
UI
0.3
UI
Transmit PLL Lock to REFCLK
TBD
TBD
ns
Notes:
23. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time.
REFCLK must be within
±
200 PPM (
±
0.02%) of the transmitter PLL reference (REFCLK) frequency, necessitating a
±
100-PPM crystal.
24. While sending continuous K28.5s, outputs loaded to a balanced 100
load, over the operating range.
25. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
operating range.
相關(guān)PDF資料
PDF描述
CYP15G0403DXB Physical Layer Devices
CYP15G0101 Single-channel HOTLink Transceiver
CYP15G0101DXB Single-channel HOTLink Transceiver
CYP15G0101DXB-BBC Single-channel HOTLink Transceiver
CYP15G0101DXB-BBI Single-channel HOTLink Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CYP15G0101DXA-BBI 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver
CYP15G0101DXB 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver
CYP15G0101DXB_11 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards
CYP15G0101DXB_12 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver
CYP15G0101DXB-BBC 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray
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