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參數(shù)資料
| 型號： | CYP15G0101DXA-BBC |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 26/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0101DXA-BBC |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 26 of 78
ceive Elasticity Buffers to be centered. While normal
characters may be output prior to this alignment event, they are
not necessarily aligned within the same boundaries that they
were transmitted.
When RXCKSEL = LOW, all four receive channels are clocked
by REFCLK. RXCLKB
+
and RXCLKD
+
outputs are disabled
(High-Z), and RXCLKA
+
and RXCLKC
+
present a buffered
and delayed form of REFCLK. In this mode, the receive Elas-
ticity Buffers are enabled. For REFCLK clocking, the Elasticity
Buffers must be able to insert K28.5 characters and delete
framing characters as appropriate. While these insertions and
deletions can take place at any time, they must occur at the
same time on both channels that are bonded together. This is
necessary to keep the data in the bonded channel-pairs prop-
erly aligned. This insert and delete process is controlled by the
channel selected using the RXCLKB+ and RXCLKD+ inputs
using the decodes listed in
Table 23
.
When RXCKSEL = HIGH, the A and B channels are clocked
by the selected recovered clock, and the C and D channels are
clocked by the selected recovered clock, as shown in
Table 23
.
The output clock for the channel A/B bonded-pair is output
continuously on RXCLKA
+
. The clock source for this output is
selected from the recovered clock for channel A or channel B
using the RXCLKB+ input. The output clock for the channel
C/D bonded-pair is output continuously on RXCLKC
+
. The
clock source for this output is selected from recovered clock for
channel C or channel D using the RXCLKD+ input.
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allowed to insert and delete
characters, except as necessary for Elasticity Buffer align-
ment.
Quad-Channel Modes
In quad-channel modes (RX modes 6 and 7, where RX-
MODE[1] = HIGH), all four receive channel output registers
must be clocked by a common clock. This mode does not op-
erate when RXCKSEL = MID.
Proper operation in this mode requires that the four transmit
data streams are clocked from a common reference with no
long-term character slippage between the bonded channels.
In quad-channel modes this means that the transmit channels
A, B, C, and D must all be clocked from a common reference.
Prior to reception of valid data, at least one Word Sync Se-
quence (or that portion of one necessary to align the receive
buffers) must be received on all four bonded channels (within
the allowable inter-channel skew window) to allow the receive
Elasticity Buffers to be centered and aligned.
When RXCKSEL = LOW, all four receive channels are clocked
by the internal derivative of REFCLK. RXCLKB
+
and RX-
CLKD
+
outputs are disabled (High-Z), and RXCLKA
+
and
RXCLKC
+
present a buffered and delayed form of REFCLK.
In this mode the receive Elasticity Buffers are enabled. For
REFCLK clocking, the Elasticity Buffers must be able to insert
K28.5 characters and delete framing characters as appropri-
ate. While these insertions and deletions can take place at any
time, they must occur at the same time on all four channels.
This is necessary to keep the data in the four bonded channels
properly aligned. This insert and delete process is controlled
by the channel selected using the RXCLKB+ and RXCLKD+
inputs using the decode listed in
Table 22
.
When RXCKSEL = HIGH, all four receive-channel output reg-
isters are clocked by the selected recovered clock. The clock
select for quad channel mode is the same as that for indepen-
dent channel operation. This selection is made using the
RXCLKB+ and RXCLKD+ inputs, as shown in
Table 22
. The
output clock for the four bonded channels is output continu-
ously on RXCLKA
+
and RXCLKC
+
.
When data is output using a recovered clock (RXCKSEL =
HIGH), receive channels are not allowed to insert and delete
characters, except as necessary for Elasticity Buffer align-
ment.
Multi-Device Bonding
When configured for quad-channel bonding (RXMODE[1] =
HIGH) it is also possible to bond channels across multiple de-
vices. This form of channel bonding is only possible when
RXCKSEL = LOW, selecting REFCLK as the output clock for
all channels on all devices.
In this mode, the BONDST[1:0] signals are used to pass chan-
nel bonding status between the different devices. This is nec-
essary to keep the data on all bonded devices in common
alignment. One device must be selected as the controlling de-
vice by driving the MASTER pin on that device LOW. All other
devices must have their MASTER pin HIGH to prevent having
multiple active drivers on the BONDST bus. Within the master
device, a single receive channel is selected as the controlling
channel for generation of the different BONDST[1:0] status.
This selection is made using the RXCLKB+ and RXCLKD+
inputs, as shown in
Table 22
. This allows the master channel
selection to be dynamically changed through external control
of the MASTER, RXCLKB+, and RXCLKD+ inputs.
Note:
Any change in master device or channel should be
followed by assertion of TRSTZ to properly initialize the de-
vices.
Output Bus
Each receive channel presents a 11-signal output bus consist-
ing of
an 8-bit data bus
a 3-bit status bus
The signals present on this output bus are modified by the
present operating mode of the PSI transceiver block as select-
ed by DECMODE. This mapping is shown in
Table 24
.
When the 10B/8B decoder is bypassed (DECMODE = LOW),
the framed 10-bit value is presented to the associated output
register, along with a status output (COMDETx) indicating if
the character in the output register is one of the selected fram-
ing characters. The bit usage and mapping of the external sig-
nals to the raw 10B coded character is shown in
Table 25
.
The COMDETx status outputs operate the same regardless of
the bit combination selected for character framing by the
FRAMCHAR input. They are HIGH when the character in the
Table 23. Dual-Channel Bonded Recovered Clock Select
RXCLKB+
0
1
X
X
RXCLKD+
X
X
0
1
Clock Source
RXCLKA
+
RXCLKA
RXCLKB
RXCLKC
+
RXCLKC
RXCLKD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0403DXB | Physical Layer Devices |
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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