參數(shù)資料
型號(hào): CYP15G0101DXA-BBC
元件分類: 通信、網(wǎng)絡(luò)模塊及開發(fā)工具
英文描述: Telecomm/Datacomm
中文描述: 電信/數(shù)據(jù)通信
文件頁數(shù): 15/78頁
文件大?。?/td> 1555K
代理商: CYP15G0101DXA-BBC
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 15 of 78
Table 6
describes the valid phase shift options that can be used
with or without an external feedback.
Table 7
is an example of the effect of all the available divide
and phase shift options on a VCO output of 250 MHz. It also
shows the effect of division on the duty cycle of the resultant
clock. Note that the duty cycle is 50-50 when a VCO output is
divided by an even number. Also note that the phase shift ap-
plies to VCO output and not to the divided output
Table 6. PLL Phase Shift Options
with and without INTCLK1 Feedback
Without External Feedback
0
°
,45
°
, 90
°
, 135
°
, 180
°
, 225
°
, 270
°
, 315
°
With External
Feedback
0
°
Table 7. Timing of Clock Phases for all Divide Options for a VCO Output Frequency of 250 MHz
Divide
Factor
1
2
3
4
5
6
8
16
Period
(ns)
4
8
12
16
20
24
32
64
Duty
Cycle%
40-60
50
33-67
50
40-60
50
50
50
0
°
(ns)
0
0
0
0
0
0
0
0
45
°
(ns)
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
90
°
(ns)
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
135
°
(ns)
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
180
°
(ns)
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
225
°
(ns)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
270
°
(ns)
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
315
°
(ns)
3.5
3.5
3.5
3.5
3.5
3.5
3.5
3.5
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