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參數(shù)資料
| 型號： | CYP15G0101DXA-BBC |
| 元件分類： | 通信、網(wǎng)絡(luò)模塊及開發(fā)工具 |
| 英文描述： | Telecomm/Datacomm |
| 中文描述： | 電信/數(shù)據(jù)通信 |
| 文件頁數(shù)： | 66/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G0101DXA-BBC |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 66 of 78
Device Control Signals
SPDSEL
3-Level Select
[37]
,
static configuration
input
Differential LVPECL
or single-ended
LVTTL input clock
Serial Rate Select. This input specifies the operating bit-rate range of both transmit and
receive PLLs. LOW = 200
–
400 MBd, MID = 400
–
800 MBd, HIGH = 800
–
1500 MBd.
REFCLK
±
Reference Clock. This clock input is used as the timing reference for the transmit and
receive PLLs. This input clock may also be selected to clock the transmit and receive
parallel interfaces. For an LVCMOS or LVTTL input clock, connect REFCLK+ to the
reference clock and leave REFCLK
–
open. For an LVPECL differential clock, both inputs
must be connected.
When TXCKSEL = LOW, REFCLK is used as the clock for the parallel transmit data
(input) interface.
When RXCKSEL = LOW, REFCLK is used as the clock for the parallel receive data
(output) interface.
Analog I/O and Control
OUTA1
±
OUTB1
±
OUTC1
±
OUTD1
±
OUTA2
±
OUTB2
±
OUTC2
±
OUTD2
±
INA1
±
INB1
±
INC1
±
IND1
±
INA2
±
INB2
±
INC2
±
IND2
±
INSELA
INSELB
INSELC
INSELD
SDASEL
CML Differential
Output
Primary Differential Serial Data Outputs. These PECL-compatible CML outputs (+3.3V
referenced) are capable of driving terminated transmission lines or standard fiber-optic
transmitter modules. These outputs must be AC-coupled for PECL-compatible connec-
tions.
Secondary Differential Serial Data Outputs. These PECL-compatible CML outputs
(+3.3V referenced) are capable of driving terminated transmission lines or standard
fiber-optic transmitter modules. These outputs must be AC-coupled for PECL-compati-
ble connections.
Primary Differential Serial Data Inputs. These inputs accept the serial data stream for
deserialization and decoding. The INx1
±
serial streams are passed to the receiver Clock
and Data Recovery (CDR) circuits to extract the data content when INSELx = HIGH.
CML Differential
Output
LVPECL Differential
Input
LVPECL Differential
Input
Secondary Differential Serial Data Inputs. These inputs accept the serial data stream
for deserialization and decoding. The INx2
±
serial streams are passed to the receiver
Clock and Data Recovery (CDR) circuits to extract the data content when INSELx =
LOW.
Receive Input Selector. Determines which external serial bit stream is passed to the
receiver Clock and Data Recovery circuit. When HIGH, the INx1
±
input is selected.
When LOW, the INx2
±
input is selected.
LVTTL Input,
asynchronous
3-Level Select
[37]
,
static configuration
input
LVTTL Input,
asynchronous,
internal pull-down
Signal Detect Amplitude Level Select. Allows selection of one of three predefined am-
plitude trip points for a valid signal indication, as listed in
Table 18
.
LPEN
All-Port Loop-Back-Enable. Active HIGH. When asserted (HIGH), the transmit serial
data from each channel is internally routed to the associated receiver Clock and Data
Recovery (CDR) circuit. All serial drivers are forced to differential logic
“
1
”
. All serial data
inputs are ignored.
Serial Driver Output Enable Latch Enable. Active HIGH. When OELE = HIGH, the sig-
nals on the BOE[7:0] inputs directly control the OUTxy
±
differential drivers. When the
BOE[x] input is HIGH, the associated OUTxy
±
differential driver is enabled. When the
BOE[x] input is LOW, the associated OUTxy
±
differential driver is powered down. When
OELE returns LOW, the last values present on BOE[7:0] are captured in the internal
Output Enable latch. The specific mapping of BOE[7:0] signals to transmit output en-
ables is listed in
Table 16
.
When the latch is closed, if the device is reset (TRSTZ is sampled LOW), the latch is
reset to enable all outputs.
OELE
LVTTL Input,
asynchronous,
internal pull-up
Frequency Agile PSI
Name
Function
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CYP15G0403DXB | Physical Layer Devices |
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0101DXA-BBI | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single Channel HOTLink II Transceiver |
| CYP15G0101DXB | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II⑩ Transceiver |
| CYP15G0101DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink II Transceiver Compliant to multiple standards |
| CYP15G0101DXB_12 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Single-channel HOTLink IIa?￠ Transceiver |
| CYP15G0101DXB-BBC | 功能描述:電信線路管理 IC Single Channel XCVR 1.5Gbps Bckplane COM RoHS:否 制造商:STMicroelectronics 產(chǎn)品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
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